System Verilog Assertion bit vector

Question

I want assertion that if in current cycle signal 'a' equal to "0110"(in binary) in the next cycle signal'b'not bigger than 31(it should be between 0 and 31.it should be less than 00000000000000000000000000011111)(its width equal 32) Can everyone help me to write assertion?! Excuse me for my bad english.

Please show what you have tried. FYI in Verilog, 0110 is read as decimal one hundred and ten; 4'b0110 is read as binary ten — Greg
– Greg, Commented Jun 29, 2016 at 18:18

Greg · Accepted Answer · 2016-06-30 00:27:31Z

1

assert property  ( @ (posedge clk )  (a == 32'b0110) |=> ( b > 32'd0 && b < 32'd32 ) );

assert - will set the property( assertion ) into action. The property has to be based on a clock . Choose the appropriate clock which is triggering the registers a & b in the design. Implication operator |=> indicates that the property has to be true in the next clock cycle. In this case if a equals 6, the next cycle b has to between 0 and 32 ).

In case of a failure some similar message ( based on the simulator ) will be displayed.

top.unnamed$$_0: started at  ns failed at  ns
    Offending '((b > 0) && (b < 32))'

You can read up a basic tutorial on assertions

https://www.doulos.com/knowhow/sysverilog/tutorial/assertions/

edited Jun 30, 2016 at 0:27

Greg

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answered Jun 29, 2016 at 22:14

Rahul Menon

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