What's the equivalent of the generic in verilog? For example
entity my_entity
generic(a : integer);
port(x : in std_logic; y out std_logic);
end entity my_entity;
What's the equivalent for generic? Also what's the equivalent for the if generate and for generate?
The generics are called parameters in Verilog. They are declared within the module by lines like:
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
An instantiation may individually refine the parameter values:
my_ram_impl #(
.DATA_WIDTH(16),
.ADDR_WIDTH(8)
)
ram_instance(
.clk(clk),
.addr(addr),
.data(data),
.cs(cs),
.we(we)
);
Use these directives similar to C for conditional synthesis:
`ifdef SYM
...
`else
...
`endif
or, more flexibly generate constructs like:
generate
if(cond)
...
else
...
endgenerate
This is an example of how to use for generate to instantiate modules, core_top in this case. NCORE is a parameter into the parent module or a localparam specifying the number of cores to instantiate.
wire clk;
wire [31:0] data_from_core[0:NCORES-1];
genvar core;
generate
for (core=0; core < NCORES; core=core+1) begin : core_gen
core_top
#(.CORE_ID (core),
.NCORES (NCORES))
u_fpgaminer_top
(.clk_in (clk),
.data_out (data_from_core[core]));
end
endgenerate
