VHDL-2008 initializing ufixed gives error in modelsim

Question

I am trying to initialize a (VHDL-2008) ufixed. But the following code gives an error in Modelsim 10.5b

entity test_e is
end entity;

library ieee;

architecture test_a of test_e is
    use ieee.fixed_pkg.all;
    constant value : ufixed(3 downto 0) := "0001";
begin
end architecture;

The error message is:

Error: [file].vhd(8): Character literal '0' of type ieee.std_logic_1164.STD_ULOGIC is not visible at the place of this string literal.

I can fix it by changing the definition line into

constant value : ufixed(3 downto 0) := to_ufixed(1,3,0);

And then when I run simulation, value holds "0001"....

I cannot figure out what I am doing wrong. I've been browsing the web for an answer, but cannot find it. Does someone know what I am doing wrong?

The declaration for std_ulogic is not directly visible here. IEEE Std 1076-2008 9.2.2 Literals para 5 - ...The type of a string or bit string literal shall be determinable solely from the context in which the literal appears, excluding the literal itself but using the fact that the type of the literal shall be a one-dimensional array of a character type. ..., para 8 - The character literals corresponding to the graphic characters contained within a string literal or a bit string literal shall be visible at the place of the string literal. Also ee 5.2.2 Enumeration types. — user1155120
– user1155120, Commented Apr 12, 2017 at 19:24
@user1155120 yes, that is what the error says. But what does "visible" mean? How should I deduct from this description that I need to explicitly include std_logic_1164 for the implicit type conversion (string->std_ulogic_vector) to work? The description must seem logic to the guys that thought it up. But for normal users, it does not hold sufficient information to fix the issue. — JHBonarius
– JHBonarius, Commented Apr 13, 2017 at 11:15
You'll likely find if you sought Modelsim help (there's a modelsim tag, too) that any documentation would use terms found in the VHDL standard and provide references. You may be underestimating the amount of knowledge of the VHDL language that's necessary to be effective using it. Visibility is defined in IEEE Std 1076-2008 12.3. There's also a glossary. It's not implicit type conversion, it's overload resolution - does the character literal represent a value of the type? The analyzer can't tell without the declaration being visible. — user1155120
– user1155120, Commented Apr 13, 2017 at 12:35
If a language gets so complicated that you often need to reference the latest IEEE standard -which notably is behind a paymentwall, and IMHO currently is 640 pages of difficult-to-comprehend language-, I think it overshot it's goal. I've been using VHDL for 18 years now, and still have to struggle with these kind of unclear exceptions. How are we supposed to teach all this to our students (I work at a University): are they supposed to learn the IEEE standard by heart or so? — JHBonarius
– JHBonarius, Commented Apr 13, 2017 at 13:29

Matthew · Accepted Answer · 2017-04-12 11:40:11Z

4

Adding an extra use statement fixes it:

entity test_e is
end entity;

library ieee;

architecture test_a of test_e is
    use ieee.std_logic_1164.all;                     -- HERE !
    use ieee.fixed_pkg.all;
    constant value : ufixed(3 downto 0) := "0001";
begin
end architecture;

Is that a bug or is it correct? I think it's correct. ufixed is declared thus:

type ufixed is array (integer range <>) of std_logic;

I'm sure you'll agree that just because you've typed use ieee.fixed_pkg.all doesn't mean you get a definition of std_logic for free. Well, I think just because you've typed use ieee.fixed_pkg.all means you don't get a definition of the std_logic literals for free, either.

answered Apr 12, 2017 at 11:40

Matthew

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8 Comments

JHBonarius Over a year ago

Hmm interesting. Same problem with numeric_std I guess. It is probably not a bug, as there are indeed ways to get it to work without loading std_logic_1164. The biggest issue is the unclear error by modelsim. I will look at what ghdl tells me.

Matthew Over a year ago

@J.H.Bonarius It's exactly the same with numeric_std - I just tried it. (I guess I've never used numeric_std without std_logic_1164. Generally, I like all inputs and outputs to be std_logic_vector and to do the type conversion on the way in and on the way out).

user1155120 Over a year ago

See the comment to the question, the declaration for std_ulogic needs to be directly visible.(A recently built) ghdl will tell you about the individual character literals not being directly visible, e.g. test_e.vhdl:8:44:error: character '0' of type std_ulogic is not visible. The Modelsim error message is accurate and descriptive. If allowed you should have had an error for each std_ulogic character literal.

JHBonarius Over a year ago

@user1155120 I disagree: i don't think it is sufficiently descriptive (else I would have found an answer myself). The error seems to indicate is compiler is aware that the type of the character should be std_ulogic. However, this gives no indication that the std_logic_1164 should explicitly be included to allow for an implicit conversion from string to std_logic_vector. It only says something vague like "not visible"... what does that mean? IMHO descriptive would be "No function prototype available to convert string to ufixed", or "type std_ulogic not defined at declaration" or so.

user1155120 Over a year ago

Your confusion might be indication the problem may be 'descriptive to whom?' Visibility has a specific meaning in VHDL, there's an entire subclause in the standard (IEEE Std 1076-2008 12.3 Visibility, the entire clause is named 12. Scope and visibility). There are concepts involved like enumeration names positionally representing values of types (5.2.2 Enumeration types), and enumeration literals can be overloaded. "function prototype" doesn't appear in the standard.

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