Import data in Verilog

Question

I would like to import data that I captured with my logic analizer using Verilog.

I dont know what would be the best way to import it to my testbench that I can test my prepared modules?

Another question is, if I should export it from logic analizer in Binary, Csv or Vdc type?

Thank you for your help!

Verilog allow to manipulate with files. So if you use verilog in logic analizer, you can write required data to file and then read the file in testbench. — Roman
– Roman, Commented Apr 20, 2017 at 9:35
I would like to display the signal that I captured with logic analizer in Vivado's simulator. — surfer113
– surfer113, Commented Apr 20, 2017 at 12:33
You need to explain how you want to use the captured data as stimulus. Is the timing to each pin critical, or just sampled data at a clock edge? And does the data represent the complete stimulus to your module (including the clock), or just one interface into your DUT? — dave_59
– dave_59, Commented Apr 20, 2017 at 12:52
I have 4 different signals, two fo them are reference and the other two are the ones that should be filtered with the module that I prepared. Timing is not important because its also changing according to input parameters. — surfer113
– surfer113, Commented Apr 21, 2017 at 5:32

Prakash Darji · Accepted Answer · 2017-04-21 07:28:49Z

1

Vivado has inbuilt feature to save the ChipScope dump, in zip format.

When you manually extract that zip file, you will have the CSV file containing all signals value.

Do modify according to your usage, read it in Verilog using file management system calls!

write_hw_ila_data my_hw_ila_data_file.zip [upload_hw_ila_data hw_ila_1]

I'm talking about that zip which is generated by this command.

Generate the zip file using this command, write_hw_ila_data my_hw_ila_data_file.zip [upload_hw_ila_data hw_ila_1]
Extract that zip file and see for waveform.csv
Convert it into xlsx to see and make any change if require
Again convert to csv, and open in testbench using file operations.

Note : Remove signal name, and extract all vectors. assign in testbench accordingly.

edited Apr 21, 2017 at 7:28

answered Apr 21, 2017 at 1:27

Prakash Darji

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6 Comments

surfer113 Over a year ago

I dont want to save anything but import signal that I captured with logic analizer and use it as my testbench!

Prakash Darji Over a year ago

To import, you have to first save it. In form of that zip, which contains CSV file. That you can open in Verilog test bench!

surfer113 Over a year ago

Aha, could you please help me with a bit more specific instructions how to do that?

Prakash Darji Over a year ago

Please download that file, and see what you have got in csv.

surfer113 Over a year ago

I am trying to use: write_hw_ila_data my_hw_ila_data_file.zip [upload_hw_ila_data hw_ila_1] but it doesnt work (error: ERROR: [Labtoolstcl 44-135] Invalid option value 'hw_ila_1' specified for 'hw_ila') . I think its because I dont have connected any hardware, but I dont need it yet for my purpose. I really dons know about which file are you talking to download. Sorry for not understanding your tips but I really appreciate your patience and help!

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