how to make std_logic_vector consist of std_logic_vectorin vhdl

Question

I have such signal:

sw : std_logic_vector(7 downto 0);

and now I want to make another one, which will have it as upper bits, 1 the rest:

std_logic_vector(31 downto 0) := (7 downto 0 => sw, others => '1');

but it won't compile. any help please? I don't want to do it bit by bit.

You haven't specified which VHDL tool, which can be important to whether or not slices are supported in aggregates using a -2008 compliant mode. That aggregate would either be (sw, others => '1') for positional association or (31 downto 24 => sw, others => '1') for named association assuming a target subtype of std_logic_vector (31 downto 0). See VHDL 2008 Just the New Stuff Peter Ashenden and Jim Lewis, 6.4 Slices in Aggregates, or IEEE Std 1076-2008, 9.3.3.3 Array aggregates. Slices in array aggregates may not be supported in your tool chain. — user1155120
– user1155120, Commented Apr 30, 2017 at 18:15

Staszek · Accepted Answer · 2017-04-30 13:27:43Z

1

I'm not entirely sure where should go this smaller signal, but you probably want to do this:

signal sw: std_logic_vector(7 downto 0);
signal big: std_logic_vector(31 downto 0);

big <= sw & x"FFFFFF";

This will assign sw vector to 8 most significant bits of big vector, and '1' to rest of bits. Write in comments, if you want to do something else.

answered Apr 30, 2017 at 13:27

Staszek

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3 Comments

Zhani Baramidze Over a year ago

I want something similar but actually sw is 6 downto 0, so it becomes little ugly your way and I prefer previous notation if possible....

Staszek Over a year ago

I don't think it is possible. You would have to assign each bit separately.

Staszek Over a year ago

Look here, there is good explanation of the topic.

JHBonarius · Accepted Answer · 2017-05-01 09:03:57Z

1

What you are trying to do is assign a signal -which is variable- to another signal during initialization. What do you expect to happen?

I.e. at the moment you define a signal, you can only initialize it. If you want to assign something to the signal, you have to write a declaration.

definition -> initialization
declaration -> assignment

So in this case you can define big a larger range, and fix the constant bits in initialization

signal big : std_logic_vector(31 downto 0) => (others => '1');

And when you want to assign sw to any part of big, do that after the begin.

big(31 downto 24) <= sw;

or

big(7 downto 0) <= sw;

etc. The bits you initialized as '1' will be overwritten by the assignment.

answered May 1, 2017 at 9:03

JHBonarius

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