How to generate a Audio sound Output on Nexys ddr 4 FPGA

Question

I want try to using Nexys 4 to generate car sound. Do i need to store the sound in ROM? what is the step to create a sound. I am using the verilog. Thanks

I'm voting to close this question as off-topic because it belongs on electronics.stackexchange.com/questions/tagged/verilog — dave_59
– dave_59, Commented May 27, 2017 at 18:37
@dave_59 Verilog is unfortunately a topic which is both present on "stackoverflow.com" and on "electronics.stackexchange.com". On both sites the same topics are discussed. — Martin Rosenau
– Martin Rosenau, Commented May 28, 2017 at 6:45
@MartinRosenau The point is that people muddle the concept of designing an FPGA with coding in a programming language. Stack overflow is for code and language issues. Electronics is for hardware issues. Verilog straddles both because it is a language for describing hardware. This question has nothing to do with the code itself — dave_59
– dave_59, Commented May 28, 2017 at 13:18

Martin Rosenau · Accepted Answer · 2017-05-28 07:20:50Z

The Nexys 4 board does not contain an audio codec but it contains a simple lowpass (or bandpass) filter creating a sound output from a PWM signal.

Your programming challenge is to create a PWM signal whose duty cycle represents the current level of the sound output signal.

I would think about the following pseudo-code (here C-like, not Verilog like):

signed int levelAccu = 0;

on_Every_Clock_Edge()
{
    int level = getCurrentSoundLevel();
    levelAccu += level;
    if(levelAccu > 0)
    {
        setOutputPin(HIGH);
        levelAccu -= MAX_LEVEL;
    }
    else
    {
        setOutputPin(LOW);
        levelAccu -= MIN_LEVEL;
    }
}

While:

getSoundLevel() represents the current desired "level" of the sound output. (The value of the current sample if you use sampled sound.)

MAX_LEVEL and MIN_LEVEL are the maximum and minimum values of the "level". Example: If you want to play sound which is stored as 8-bit signed values you have MAX_LEVEL=127 and MIN_LEVEL=-128.

The register levelAccu should have 1 or 2 bits more than the level.

Note that the clock edges must be much faster than the sample rate of the audio.

Do I need to store the sound in ROM?

Depends on which kind of sound you want to create.

If you want to play recorded sound samples you'll have to store them in some memory (RAM, ROM...).

If you want to generate sound programmatically (such as sine waves) you don't have to store them.

By the way

Your question is not Verilog specific but it is more related to FPGAs in common and to the circuits close to the FPGA.

For this reason "electronics.stackexchange.com" should really be the better place for such questions.

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