How to derive a Fixed Length Output signal from a variable length Input signal in verilog

Question

I have an HDL Block in which the output follows the input in such a way that when input signal is binary 0, output remains 0 but when input turns 1, output turns 1 for a preset number of clock cycles (signal_length). i.e. input may remain high for suppose 65 or 66 clock cycles but output should remain high for preset number of clock cycles. I tried to accomplish the task with Verilog. But I am having an error and I don’t know how to rectify. Hope someone can help.

module last_ind
#(
parameter MAX_LENGTH = 262144,
parameter signal_length
)
(
   input           clk,      
   input [17:0] pkt_length,
   input           tdata,
   output          tlast
);
reg [17:0] cnt = 0;

always @ (posedge clk)
begin
if ((tdata==1) && (cnt<signal_length)) 
        tlast <= 1;
 else
        cnt <= 0;
 end
 assign   cnt <= cnt + 1'b1;
 endmodule

Your if statement is just not correct. If you write out the behavior explicitly in a way that makes sense to you, transcribing it into code is pretty easy. Some questions to help: When do you want to set tlast to 1? When do you want to set it back to 0? Do you need to reset cnt to zero redundantly? Do you need to increment the counter on every cycle? What happens if the counter overflows while the input is held high? — Zalman Stern
– Zalman Stern, Commented Oct 6, 2017 at 8:00
Verilog is a hardware description language - it is intended to model hardware and so all happens at once. The lines of code between module and endmodule are not executed sequentially. Consequently, this line is nonsense: assign cnt <= cnt + 1'b1;. Presumably, you want to increment your counter each clock cycle, If so, you need to put this line inside an always @(posedge clk) block. — Matthew
– Matthew, Commented Oct 6, 2017 at 8:21
I want tlast to remain 0 when input tdata is 0 and when tdata turns 1, output tlast should turn 1 immediately. Input tdata will remain 1 for 65 clock cycles but tlast should remain 1 for 63 clock cycles and change to 0 after 63 clock cycles. counter should increment every clock cycle and when it reaches 63, it will force tlast to become 0 after this counter can reset to 0 and should remain zero until tdata is 0(which will remain 1 for 2 more clock cycles(65-63 cycles). counter should remain 0 when tdata is zero and counter can start when tdata becomes 1 once again. — H.K
– H.K, Commented Oct 6, 2017 at 8:23
That seems to be a good start of a description. It might be good to explicitly note which things are guaranteed about the input (e.g. tdata is only high for between 63 and 65 cycles) and which things this code has to guarantee. Taking into account Matthew Taylor's and noting that the code above never sets tlast to 0, can you start to make progress? What is the relationship of signal_length to these numbers 63 and 65? What happens in setting the counter to 0 when it reaches signal_length if tdata is still high at that time? — Zalman Stern
– Zalman Stern, Commented Oct 6, 2017 at 8:51

Serge · Accepted Answer · 2017-10-08 23:19:05Z

1

maybe something like this will do. It should keep the signal up for the signal_length cycles and will reset when tdata gets '0'. You decide on the correct protocol though.

 reg [17:0]      cnt = signal_length;

 always @ (posedge clk) begin
    if (cnt < signal_lenth)
      cnt <= cnt + 1;
    else if (cnt == signal_length + 1 && tdata == 1 && tlast == 0) begin
      cnt <= 0;
      tlast <= 1;
    end
    else if (tdata == 0) begin 
       cnt <= sighal_length + 1;
       tlast <= 0;
    end
    else
       tlast <= 0;
end

edited Oct 8, 2017 at 23:19

answered Oct 7, 2017 at 16:31

Serge

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2 Comments

H.K Over a year ago

Thanks for your response. I have changed my code as per your suggestion however I still have a problem. Tlast becomes 0 when the cnt is 63 as per the expectations but turns to 1 again after next clock cycle (because tdata is still 1). However Tlast should remain 0 until tdata takes a complete transition from 1-0-1 and the cycle should start again. i.e. to say that Tlast is 1 for 63 cycles only irrespective of the length of tdata and restarts the cycles when tdata turns to 0 and then a subsequently transits to 1.

Serge Over a year ago

I did a fix in the example. This should wait till tdata gets 0 before continuing. Sorry, i did not test it. There are just ideas of the syntax which you can use. There are other implementations for this as well. Try your own.

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