How to modify initialization done by modelsim?

Question

My question is related to the initialization done by modelsim. I want to use integer in a particular range (range 0 to 511 for example). Here is the declaration in VHDL:

signal cnt : natural range 0 to 511;

If I do not initialize this signal (in a reset for example), modelsim will assign the leftmost value by default. For my signal, it would be 0.

My problem is I would like to force modelsim to initialize its value in simulation to 'U' or 'X' instead of the leftmost value, is it possible ?

A natural is a numeric type. 'U' and 'X' are not possible. — JHBonarius
– JHBonarius, Commented Jul 25, 2018 at 15:47

Renaud Pacalet · Accepted Answer · 2018-07-25 11:21:46Z

2

Signals can be given an initialization value at declaration:

signal foo: foo_type := foo_type_value;

Note the := assignment operator which may look a bit counter-intuitive for a signal.

But no, it is not possible to assign 'U' or 'X' to a signal which type is natural because they are not natural values. What you can do, instead, is decide that value 512 is the equivalent of U for your signal and assign it at declaration time:

signal cnt : natural range 0 to 512 := 512;

As this extra value is not supposed to be used after initialization you could (should) add a concurrent assertion to detect unwanted situations:

assert cnt /= 512 report "Ooops! cnt=512" severity warning;

Another option is to use ieee.numeric_std.unsigned instead of natural:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...
signal cnt : unsigned(8 downto 0) := (others => 'U');

But before using this, be sure you understand the differences. For instance, if you try to decrement your natural cnt while its value is 0 you will get an error while with the unsigned version cnt will silently wrap to "111111111".

edited Jul 25, 2018 at 11:21

answered Jul 25, 2018 at 9:55

Renaud Pacalet

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4 Comments

Matthieu Over a year ago

Hi Renaud, Thank you for taking time to answer. My question was not clear. When we use integers with a range which are not initialized, the simulation tool (I am using modelsim) assign the leftmost value of the range to them. I would like to know if it is not possible to change this rule and to give a random value when "ranged" integers are not initialized (I did not fing in modelsim.ini). Some ranged signals are not initialized in my design and take the leftmost value which is always 0. The problem is we don't know which value the synthetizer will assign to these uninitialized signals

Renaud Pacalet Over a year ago

I think I understood your point. But if the initialization values are important, why don't you use a reset to properly force all your internal registers to a pre-defined (and constant) value? You would then start your simulation with a reset phase and you would be guaranteed that the hardware will behave as your simulation did (if the hardware is also reset after power up, of course). And the initialization value of your signals would not be relevant any more.

JHBonarius Over a year ago

@Matthieu can you please clearify this in your question. What do you really want to achieve in the end.

Paebbels Over a year ago

It is not a rule of your simulator it's it is a rule in VHDL that all objects get initialized with the left-most value: T'left, where T is the subtype used to declare the object: O'subtype'left. Synthesizers and simulators have the same behavior accept for type std_logic, which gets reduced to 01Z.

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