SystemVerilog: Automatic variables cannot have non-blocking assignments appearing for static reg

Question

I start getting this error after I actually make a register static.

This complies fine in Quartus:

task InitAutoRefresh;

       reg [$clog2(AUTOREFRESH_CLOCKS):0] AutoRefreshCounter = 0;

       AutoRefreshCounter <= AutoRefreshCounter + 1;
       InitState <= (AutoRefreshCounter < AUTOREFRESH_CLOCKS) ? InitState : InitState + 1;       

       InitCmd <= (AutoRefreshCounter == 0) ? CMD_AR : CMD_NOP;

endtask

But Modelsim gives me this error:

# ** Error (suppressible): C:/projects/Camera-RAM-VGA/Ram.sv(137): (vlog-2244) Variable 'AutoRefreshCounter' is implicitly static. You must either explicitly declare it as static or automatic
# or remove the initialization in the declaration of variable.

Now when I add static in front of reg [$clog2(AUTOREFRESH_CLOCKS):0] AutoRefreshCounter = 0; Quartus gives me this error (which looks to be the opposite of my change):

Error (10959): SystemVerilog error at Ram.sv(139): illegal assignment - automatic variables can't have non-blocking assignments

And this points to the register that I've just added the static keyword for!

The only possible explanation I can think of is that when I add static to this single reg it starts treating other regs as automatic, but then the line number in the error message is wrong.

dave_59 · Accepted Answer · 2018-09-17 22:46:23Z

2

I would simply move the declaration of AutoRefreshCounter outside of the task. Then it is clear that the variable is to be initialized only once at time 0. (That is the reason for the "Implicitly static" error message in the first place).

edited Sep 17, 2018 at 22:46

answered Sep 17, 2018 at 22:41

dave_59

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1 Comment

axk Over a year ago

This is what I ended up doing for now. I wanted to keep it inside the task for code re-used. I'm a newbie and Verilog is giving me a hard time with my attempts of code re-use (like I would do in procedural programming)

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