Timing issues while synthesizing a design in Verilog

Question

I am working on a Decoder module based on BCH codes. The design is to be implemented on a Virtex-7 FPGA . I have basically three blocks . Syndrome computation block , Error locator finder and Error locator solver block . The syndrome computation block is working fine on the FPGA and it is working at 225 MHz clock . I am working on the Error locator finder block and it is giving me some timing issues. The problem is essentially this :

1) I have a module that has just a case statement . The case block has 1024 entries . The path that is failing contains this module . If I comment out this module , the design works fine . In the implemented design , this module is placed too far and because of this , I am getting a huge net/wire delay. Is there a way for me to have the case based module closer to my actual design ??

Any help will be appreciated. The net delay accounts for atleast 60 percent of the total delay . This is unacceptable for the problem I am trying to solve as this decoder needs to work atleast at 200 MHz

The normal procedure is to add a pipeline stage in the failing path. I know, that might require a major re-design of all adjacent path logic, but it is the way to go. — Oldfart
– Oldfart, Commented Feb 13, 2019 at 10:24

ttobsen · Accepted Answer · 2019-03-07 13:40:16Z

In the previous Xilinx FPGA tool suite called ISE, you had the ability to vary the Placer Cost Table (PCT), which results in different location placement of the logic cells which leads to varying timing results. The PCT could be iterated in different implementation runs (using SmartXplorer) which where stopped until a PCT was found with valid timing results.

Xilinx dropped this strategy due ineffectiveness in large FPGAs (like your Virtex 7 device is). But you have several predefined strategies which also can be run in parallel. Just open the Implementation Settings and try different strategies and see if one is working.

If not, you have to optimize your design on HDL level. In general, pipelining is a good strategy, but it depends strongly on your code. In general you have to reduce large combinational constructs and your case statement with 1024 entries is such a candidate of a large combinational construct.

Edit: See Xilinx UG904 to get an overview and a brief description of the different implementation strategies.

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