Inferring Latch in a nested If-Else statement (VHDL)

Question

I have a problem with an inferred latch with my code. I know a latch is usually caused by not having all situations for an output accounted for, but in this situation, I haven't seen any online examples that cover this. I have a nested if-else statement in a process statement as shown below. Just to quickly explain what I'm doing, after a reset is initiated, reset_cnt will go high and initiate a counting process for sck up to 24 cycles and repeat itself and output will increment.

clock_counter: process(reset, sck, counter, output, reset_cnt, reset_done)
begin
  if (reset = '1') then
    counter <= 0;
    output <= 1;
    reset_cnt <= 1;
    reset_done <= '1';
  else
    reset_done <= '1';   -- added to fix
    reset_cnt <= 1;      -- added to fix
    output <= output;          -- added to fix (didn't work)
    if (reset_cnt AND counter = 24) then
      counter <= 0;
      output <= output + 1;
    elsif (rising_edge(sck)) then
      counter <= counter + 1;
    end if;
  end if;
end process;

Originally I had a problem with 3 latches: reset_done, reset_cnt, and output. I added in some lines of code (the ones with the comments next to it) and I was able to remove latches for reset_done and reset_cnt. It looks like I still get an inferred latch for out because I use it in the nested If statement. I thought:

output <= output;

might work, but I guess not. Does anyone know how to fix this kind of latch? I should mention, I've tried splitting this up into 2 process statements, and making it into a case statement, but that didn't work either. Any help or advice is much appreciated!

Have a look at this answer here.

Matthew
– Matthew

2019-02-22 09:30:23 +00:00
Commented Feb 22, 2019 at 9:30 — Matthew
– Matthew, Commented Feb 22, 2019 at 9:30

Paebbels · Accepted Answer · 2019-02-22 12:04:03Z

4

This code is totally wrong. It's hard to fix because it combines multiple mistakes in one process.

I'll try to enumerate some of your mistakes:

The sensitivity list should not use output and reset_done.
output <= output + 1; cannot be synthesized or will create an endless loop in simulation
you need to distinguish combinational and sequential logic into two processes
reset_done and reset_cnt are useless, because they are always '1'
reset_cnt is an integer, this cannot be ANDed with a boolean from expression counter = 24
never write output <= output;

I suggest to study about combinational and sequential processes as well as coding patterns for VHDL.

edited Feb 22, 2019 at 12:04

answered Feb 21, 2019 at 23:53

Paebbels

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1 Comment

Namit Patel Over a year ago

You're right, I was in such a rush to get this done, I was ignoring the basics of FPGA design. I'm starting this from scratch following proper design guidelines.

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