Verilog - Output of a module staying in unknown state when simulated

Question

When I try to simulate a module using Quartus prime's Simulation Waveform editor, the output of the module stays in the unknown state or don't care state ('X'). The module is the only one in the project along with the .vwf file.

Here is the module:

module pc (input clk, reset_n, branch, increment, input [7:0] newpc,
            output reg [7:0] pc);


parameter RESET_LOCATION = 8'h00;

    initial pc = 8'h00;

    always @(posedge clk or posedge reset_n) begin

        if (reset_n) begin

            pc <= RESET_LOCATION;

        end else begin

            if (increment) begin
                pc <= pc + 1;
            end else if (branch) begin 
                pc <= newpc;
            end 

        end

    end

endmodule

And here is the simulation:

@toolic you're right it's supposed to be active low.

alexanderd5398
– alexanderd5398

2019-03-25 18:36:34 +00:00
Commented Mar 25, 2019 at 18:36 — alexanderd5398
– alexanderd5398, Commented Mar 25, 2019 at 18:36

alexanderd5398 · Accepted Answer · 2019-03-25 18:30:18Z

0

I found the solution...

I am not sure why, but I need to create a new .vwf whenever I change the top level entity.

answered Mar 25, 2019 at 18:30

alexanderd5398

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