How to initialize a wire[4:0] array in Verilog?

Question

I want to initialize a 5-bit wire with a constant. How to do that in Verilog?

wire [4:0] master_data_out = [1'b0, 1'b1, 1'b1, 1'b0, 1'b0];

5 bit is fine. I reduced it from 64 to simplify for the question. — Neil Dey
– Neil Dey, Commented Apr 30, 2019 at 22:10

Christian B. · Accepted Answer · 2019-04-30 23:18:54Z

3

Maybe you are looking for

wire [4:0] master_data_out = 5'b01100;

or

wire [4:0] master_data_out = {1'b0, 1'b1, 1'b1, 1'b0, 1'b0};

BTW a simple web search would have yield that very basic concept mostlikely very quickly.

answered Apr 30, 2019 at 23:18

Christian B.

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