How do I access internal regs/signals without declaring them as input/output. e.g., consider the following block, A & B are placed in TOP block and I need to access int_A from withing block B without declaring it as output in A and input in B.
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To the best of my knowledge there is no way (and I would be actually shocked if there is one, as it would mean that "sideeffects" could be implemented which implies serious testablity issues). Could you elaborate why "exposing" int_T is not an option for you?Christian B.– Christian B.2019-05-15 10:22:18 +00:00Commented May 15, 2019 at 10:22
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Well, I am creating a block which has both digital and analog blocks. in order to model the analog block i need to create element which do not really exist in the analog. e.g. say the analog block has an output voltage output. This output it a 'single bit' from the analog part. However inside the analog block MODEL I use a 'real' or bus to represent the voltage. i do not want to add extra outputs to the analog block, in this case the representation of the voltage.dandan– dandan2019-05-15 10:52:18 +00:00Commented May 15, 2019 at 10:52
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1 Answer
You can do that by hierarchical reference.
However as far as I know you can only use that in test-benches.(I have never even dared to use that in RTL).
// Top level test-bench
wire int_A;
assign int_A = dut_0.int_A;
dut dut_0 ( // instance of dut
....
);
If inside the dut you have another instance use the same method:
module dut (
);
core core0 (
);
endmodule // dut
A signal inside the core can now be referenced from the top level as:
assign int_A = dut_0.core_0.int_A;
2 Comments
dandan
so the way to do this, in my case, since A & B are under the TOP, is to use 2 statements? 1 in the top to reference the wire in Block A, and 1 in block B to reference the wire (reference) in A? Is there a way to use only 1 definition, inside block B which references a wire in A? Both A & B are under TOP.
Oldfart
I think you can do a full path reference form anywhere in the design. Thus in B you can use
top.A.int_A.