Segmentation fault: 11 while compiling with yosys

I'm trying to implement a Verilog module that writes in a Lattice UP5K SPRAM hardware core using the Yosys SB_SPRAM256KA block. Note that there are little or no documentation/examples about usage of this black box block. The main purpose is implementing an echo or delay in an audio digital system.

I have two clocks the frame clock lrclk and the bit clock bclk, note that each period of frame clock has 64 bit clocks periods.

I tried to, with a sensitivity list in the blck, cycle a read/write process in the SPRAM. I implement a state machina that:

• S1: Put the input data in the input port of the RAM, enable the write_enable signal and set the writing pointer to RAM address.
• S2: (Data supposed to be written) Disables write_enable signal and set the reading pointer to RAM address.
• S3: (Data supposed to be loaded on output buffer of the RAM). Set the module output from the RAM output buffer and resets the state machine.

This is the module code:

module echo(    
    input wire bclk,
    input wire lrclk,

    input wire [DATALEN-1:0] right_in,
    output reg [DATALEN-1:0] right_out,
);

localparam ADDRLEN = 14;
localparam DATALEN = 16;

reg [ADDRLEN-1:0] rd_ptr = 0;
reg [ADDRLEN-1:0] wr_ptr = (2**ADDRLEN)/2;

reg [2:0] sm = 0;

reg wren;
reg [ADDRLEN-1:0] memaddr;
reg [DATALEN-1:0] datain;
reg [DATALEN-1:0] dataout;

SB_SPRAM256KA M1 (
    .ADDRESS(memaddr),
    .DATAIN(datain),
    .MASKWREN(4'b1111),
    .WREN(wren),
    .CHIPSELECT(1'b1),
    .CLOCK(bclk),
    .STANDBY(1'b0),
    .SLEEP(1'b0),
    .POWEROFF(1'b0),
    .DATAOUT(dataout)
  );

always @(posedge lrclk) begin
    sm <= 1;
end

always @(posedge bclk) begin
    if (sm === 1) begin
        datain <= right_in;
        wren <= 1;
        memaddr <= wr_ptr;
        sm <= 2;
    end else if (sm === 2) begin
        wren <= 0;
        memaddr <= rd_ptr;
        sm <= 3;
    end else if (sm === 3) begin
        right_out <= dataout;
        wr_ptr <= (wr_ptr + 1);
        rd_ptr <= (rd_ptr + 1);
        sm <= 0;
    end
end

endmodule

I expect to have errors on systhesis time or misfunctional behaving of the implementation, but I obtain this Yosis error:

5.11. Executing WREDUCE pass (reducing word size of cells).
Removed top 31 bits (of 32) from port B of cell main.$add$main.v:70$2 ($add).
Removed top 1 bits (of 32) from port Y of cell main.$add$main.v:70$2 ($add).
Removed top 2 bits (of 3) from FF cell main.$techmap\E1.$procdff$117 ($dff).
make: *** [main.bin] Segmentation fault: 11