Getting error in primitive output connection must be a scalar var or net

Question

I am a beginner in using HDL and have made several basic modules in Verilog. Now today, while creating one of my project in Verilog I got this strange error on line 5:

primitive output connection must be a scalar var or net

I don't have any clue how to solve this.

I tried changing the buffer module to xor module, but no change was observed.

module decoder(A, B);
    input[1:32] A;
    output[1:38] B;
    buf p1(B[3:3], A[1:1]);
    buf p2(B[5:7], A[2:4]);
    buf p3(B[9:15], A[5:11]);
    buf p4(B[17:31], A[12:26]);
    buf p5(B[33:38], A[27:32]);
    xor u1(B[1], A[3], A[5], A[7], A[9], A[11], A[13], A[15], A[17], A[19], A[21], A[23], A[25], A[27], A[29], A[31]);
    xor u2(B[2], A[3], A[6], A[7], A[10], A[11], A[14], A[15], A[18], A[19], A[22], A[23], A[26], A[27], A[30], A[31]);
    xor u3(B[4], A[5], A[6], A[7], A[12], A[13], A[14], A[15], A[20], A[21], A[22], A[23], A[28], A[29], A[30], A[31]);
    xor u4(B[8], A[9], A[10], A[11], A[12], A[13], A[14], A[15], A[24], A[25], A[26], A[27], A[28], A[29], A[30], A[31]);
    xor u5(B[16], A[17], A[18], A[19], A[20], A[21], A[22], A[23], A[24], A[25], A[26], A[27], A[28], A[29], A[30], A[31]);
    xor u6(B[32], 0, A[32]);
endmodule

The simulation is not running, and it gives this error.

Oldfart · Accepted Answer · 2019-09-14 07:08:48Z

2

Verilog built-in primitives are split into groups each with a specific number of input and output ports.

and nand or nor xor xnor have one output and multiple inputs.
buf and not have multiple outputs and one input.

_{(There are more types like enable gates and pass gates but let's leave those for now)}

Thus a buf instance must be buf <name> (output, output, output,... input);
Thus a xor instance must be xor<name> (output, input, input, input ...);

As you can see your p2(B[5:7], A[2:4]); does not follow this rule as you have three inputs: A[2:4].

As a side note: It is customary to index vectors from high to low: B[13:8]and also go from high to zero: input [31:0] value,. What you do is not wrong but it makes life more difficult if your code has to work together with established code.

answered Sep 14, 2019 at 7:08

Oldfart

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1 Comment

toolic Over a year ago

It is also important to note that each bit must be separated by a comma. This is illegal: buf (B[3:5], A[2]);. But, this is legal: buf (B[3], B[4], B[5], A[2]);.

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