Proper way to use a bus in a for loop in SystemVerilog?

Question

I'm trying to make a module in SystemVerilog that can find the dot product between two vectors with up to 8 8-bit values. I'm trying to make it flexible for vectors of different length, so I have an input called EN that's 3 bits and determines the number of multiplications to perform.

So, if EN == 3'b101, the first five values of each vector will be multiplied and added together, then output as a 32-bit value. Right now, I'm trying to do that like:

int acc = 0;

always_comb
begin
for(int i = 0; i < EN; i++) begin
    acc += A[i] * B[i];
    end
end
assign OUT = acc;

Where A and B are the two input vectors. However, SystemVerilog is telling me there's an illegal comparison being performed between i and EN.

So my questions are:

1) Is this the proper way to have a variable vector "length" in SystemVerilog?

2) If so, what's the proper way to iterate n times where n is the value on a bus?

Thank you!

Welcome to Stack Overflow. Please post a minimal reproducible example so someone else can reproduce your error. (At the moment your code looks fine, but it is not compilable so no one can check and see for themselves.) — Matthew
– Matthew, Commented Nov 27, 2019 at 9:20
The "proper way" depends on whether you need these different sizes to be available in one piece of hardware or whether you want one block of code to be customisable so that it can be reused to produce various pieces of hardware, each of which can multiple vectors of a single (but customisable) size. — Matthew
– Matthew, Commented Nov 27, 2019 at 9:21

RookieHere · Accepted Answer · 2019-11-27 14:20:11Z

I have to guess here, but I'm assuming it's a synthesizer complaining about that code. The synthesizer I use accepts your code with minor modifications, but maybe not all do since the loop can't be unrolled statically (notice I have input logic [2:0] EN, maybe input int EN does not work due to having too big a max number of cycles). Your loop per se (question #2) is fine.

int acc;
always_comb
begin
// If acc is not reset always_comb tries to update on its old value and puts
// it in sensitivity list, halting simulation... also no initialization to variable
// used in always_comb is allowed.
acc = 0;
...

This is a somewhat decent reason to complain about your otherwise perfectly good code, and the tool does not make the assumption that it is "reasonable" to generate all possible loops in this specific case (if EN was an unsigned integer your chip would be stupidly huge after all): you can force the tool to infer all possibilities with something that looks like the following:

module test (
    input int A[8],
    input int B[8],
    input logic [2:0] EN,
    output int OUT
);

    int acc[8];  // 8 accumulators

    always_comb begin
        acc[0] = A[0] * B[0];  // acc[-1] does not exist, different formula!
        for (int i = 1; i < 8; i++) begin
            // Each partial sum builds on previous one.
            acc[i] = acc[i-1] + (A[i] * B[i]);
        end
    end

    assign OUT = acc[EN];  // EN used as selector for a multiplexer on partial sums

endmodule: test

The above module is an explicit description of the "parallel loop" my synthesizer infers.

Regarding your question #1, the answer is "it depends". In hardware there is no variable length, so unless you fix the number of iterations as a parameter as opposed to an input you either have a maximum size and ignore some values or you iterate over multiple cycles using pointers to some memory. If you want to have a variable vector length in a test (not going to silicon) then you can declare a "dynamic array" that you can resize at will (IEEE 1800-2017, 7.5: Dynamic arrays):

int dyn_vec[];

As a final side note, int bad integer good for everything that is not testbench in order to catch X values and avoid RTL-synthesis mismatch.

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