Passing bus to another module via port mapping in SystemVerilog

Question

I have below code inside SV module, where I instantiate another SV module and pass 5-bit bus to it to check for X and Z's as coded below:

  input  [4:0] analdo_trim; 
  cds_XZ_checker XZ_check_analdo_trim (.in(analdo_trim),.in_ok(analdo_trim_ok));

Here is module definition for cds_XZ_checker:

module cds_XZ_checker(in,in_ok);
input in;
output bit in_ok;

always_comb  begin              //Asynchronous assertion check block
      asynch_XZ_check: assert (!($isunknown(in))) in_ok=1'b1; 
        else begin 
            $warning ("WARNING (%M) digital signal in=%b is undefined at time %t",in,$time); 
            in_ok=1'b0;
        end//else
end

endmodule

The issue is when I read 5-bit analdo_trim in above module via in port, it only reads LSB of analdo_trim. Any ideas why the whole 5-bit array is not being passed with above syntax?

toolic · Accepted Answer · 2021-12-20 22:24:41Z

2

You declared the module input to be 1-bit wide. You need to declare it as 5-bit wide. Change:

input in;

to:

input [4:0] in;

answered Dec 20, 2021 at 22:24

toolic

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Comments

Erling Olsen · Accepted Answer · 2021-12-20 22:40:43Z

0

Now 5-bit bus to it to check for X and Z's it will be passed. Yours was a small mistake in the declaration

module cds_XZ_checker(in,in_ok);
input [4:0] in; 
output bit in_ok;

always_comb  begin              //Asynchronous assertion check block
      asynch_XZ_check: assert (!($isunknown(in))) in_ok=1'b1; 
        else begin 
            $warning ("WARNING (%M) digital signal in=%b is undefined at time %t",in,$time); 
            in_ok=1'b0;
        end//else
end

endmodule

answered Dec 20, 2021 at 22:40

Erling Olsen

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