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This is a question about the vector extension in RISC-V. Currently, I'm considering adapting my custom RTOS to support the vector extension.

Upon reviewing the spec for the vector extension, I've learned that the size of vector registers depends on vlen. When performing a context swap of vector registers between tasks, if vlen is 64 bits or less, it would suffice to execute the vle64.v instruction 31 times (excluding v0). However, if vlen is 2048 or 4096, the time required for context swapping of vector registers becomes immense.

If managing context on a per-task basis, it can be anticipated that significant time will be consumed for context swapping every time a task switches. In vector extension version 1.0-rc2-draft, it's explained that the mstatus.VS field is provided to avoid unnecessary context swaps. However, context swapping cannot be avoided when switching tasks because each task has its own context, making context swapping necessary.

So, how should one go about performing context swaps for the vector extension?

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There are some importants to consider:

  1. Ultimately, if there are multiple tasks using vector registers then there is no other option than to save and restore vector context when context switching between those tasks.

  2. The use of vector instructions and registers is relatively uncommon in the general case.

  3. As a result of 1 and 2, operating system kernels tend to manage vector register context only if there is evidence that the user-space process/thread is actually using vector registers. If not, there is no need to save/restore the vector registers and hence no cost.

The way this is supposed to work with RISC-V's 'V' extension is, as you have noticed already, dependent on the use of the mstatus.VS bitfield.

The algorithm would be akin to:

  1. When the task is created, mstatus.VS is set to 'Off'.

  2. If the task attempts to use vector registers the processor will get an illegal instruction exception.

  3. In response to 2, the OS kernel sets some state in the task's control block signifying that it has used vector registers. The task is then allowed to proceed.

  4. When it is time to switch away this task's context (timeslice expiry/interrupt etc), the state in 3 is used to determine whether the vector register context needs to be saved within the task's context data structure or not.

The above is what is essentially meant by 'Software will typically use VS to reduce context-swap overhead' in the RISC-V 'V' spec.

Hope that helps.

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Further, perhaps mstatus.VS can be turned off on context switch to a process previously using them as well — meaning a process will get that illegal instruction exception again, this time for reloading them. It could be up to the OS to decide whether to swap them in on context switch and turn mstatus.VS on, or turn off mstatus.VS, dynamcally so that a process that uses them rarely becomes less expensive to swap in/out.
If you set the VS field to OFF and use exception handling to detect access to vector extension resources, how can you determine if the exception that occurred is due to "access to vector extension resources"? It's possible to infer from the opcode stored in mtval at the time of exception occurrence, but honestly, detecting access to vector CSRs using instructions like csrr would be quite impossible. If the vector extension had provided a cause for "illegal instruction execution exception due to access to vector extension resources" in mcause, such issues wouldn't have arisen.

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