Padding zeros with std_logic_vector results in Implementation Error

Question

I'm encountering an issue with Vivado where zero-padding in my VHDL code is not being preserved in the elaborated design and results in Implementation Error. Here's a brief overview of the problem:

I have a 14-bit counter in my VHDL design, and I need to concatenate it with zeros to form a 32-bit signal before assigning it to a RAM input. I achieved this using the following code snippet:

ram_input <= "000000000000000000" & i;

Here is the elaborated design snapshot, where zeros are missing to make ram_input 32-bit wide, it just take counter i (14-bits) value:

In simulation, everything works as expected, and the counter value is correctly padded with zeros. However, in the elaborated design generated by Vivado, only the 14 bits of the counter seem to be considered, disregarding the zero-padding.

Has anyone else encountered a similar issue with Vivado or other synthesis tools? Are there any specific settings or techniques I should be aware of to ensure that zero-padding is preserved in the elaborated design?

I want to expect suggested way to append zeros with i (std_logic_vector) to make it 32-bit wide and could see the block in Elaborated Design. Now, it just take counter i value as an Input.

Synthesis tools remove all unused or constant logic to keep the design as small as possible. So you will not see signals which are clamped at 0 or 1 in your netlist. But of course the design will behave as simulated. — Matthias Schweikart
– Matthias Schweikart, Commented Mar 25, 2024 at 12:11
But, I'm more interested in Implementation part. How can I implement this logic to make it 32 bit wide by appending zeros at MSB locations with counter i, having 14 bits output value. — Abbas Ali
– Abbas Ali, Commented Mar 25, 2024 at 18:39
If you read back the 32 bit value, it will be padded with zeros — Tricky
– Tricky, Commented Mar 25, 2024 at 23:30

M Safeer · Accepted Answer · 2024-04-05 01:47:23Z

0

There are a couple of things that you can try. First, using the dont_touch attribute on the input and output registers should work. Secondly, you can use the Out of Context mode to synthesize your design. This will preserve every module ports and you will be able to implement it as you intend.

answered Apr 5, 2024 at 1:47

M Safeer

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