What is wrong with the array constant declaration in my VHDL code?

Question

I am a digital technology student trying to learn VHDL.

I wrote this testbench code for 4 bit bcd adder to 7 segment display

I have tried all the possibilities i and chat GPT could think of but the compiler still gave me the same error

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BCD_Adder_7Segment_tb is
end BCD_Adder_7Segment_tb;

architecture Behavioral of BCD_Adder_7Segment_tb is

    -- Component declaration for the DUT (Design Under Test)
    component BCD_Adder_7Segment is
        Port (
            A, B : in BIT_VECTOR(3 downto 0);
            Cin : in BIT;
            Sum : out BIT_VECTOR(3 downto 0);
            Cout : out BIT;
            SEG_A, SEG_B, SEG_Sum : out STD_LOGIC_VECTOR(6 downto 0)
        );
    end component;

    -- Testbench signals
    signal A_tb, B_tb, Sum_tb : BIT_VECTOR(3 downto 0);
    signal Cin_tb, Cout_tb : BIT;
    signal SEG_A_tb, SEG_B_tb, SEG_Sum_tb : STD_LOGIC_VECTOR(6 downto 0);

   
         constant  TableArray : array (0 to 15) of STD_LOGIC_VECTOR (3 downto 0) := (
        "0000", "0001", "0010", "0011",
        "0100", "0101", "0110", "0111",
        "1000", "1001", "1010", "1011",
        "1100", "1101", "1110", "1111" );

begin

    -- Instantiate the DUT
    DUT : BCD_Adder_7Segment
        port map (
            A => A_tb,
            B => B_tb,
            Cin => Cin_tb,
            Sum => Sum_tb,
            Cout => Cout_tb,
            SEG_A => SEG_A_tb,
            SEG_B => SEG_B_tb,
            SEG_Sum => SEG_Sum_tb
        );

   -- Stimulus process
    stimulus_process: process
        variable F1 : bit;
    begin
        -- Initialize inputs
        A_tb <= "0000";
        B_tb <= "0000";
        Cin_tb <= '0';

        -- Test all possible combinations of A, B, and Cin
        for i in 0 to 15 loop
            for j in 0 to 15 loop
                for k in 0 to 1 loop
                    case k is
                        when 0 =>
                            F1 := '0';
                        when 1 =>
                            F1 := '1';
                    end case;

                    A_tb <=  TableArray (i);
                    B_tb <=  TableArray (j);
                    Cin_tb <= F1;

                    -- Apply stimulus
                    wait for 10 ns;
                end loop;
            end loop;
        end loop;

        wait;
    end process stimulus_process;

end Behavioral;

`

the error states

vcom -work work -2002 -explicit -stats=none F:/Softwares/BCD_Adder_7Segment_tb.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 2021.1 Compiler 2021.02 Feb  3 2021
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity BCD_Adder_7Segment_tb
-- Compiling architecture Behavioral of BCD_Adder_7Segment_tb
** Error: F:/Softwares/BCD_Adder_7Segment_tb.vhd(26): near "array": (vcom-1576) expecting STRING or IDENTIFIER or << or '('.
** Error: F:/Softwares/BCD_Adder_7Segment_tb.vhd(67): (vcom-1136) Unknown identifier "TableArray".
** Error: F:/Softwares/BCD_Adder_7Segment_tb.vhd(68): (vcom-1136) Unknown identifier "TableArray".
** Note: F:/Softwares/BCD_Adder_7Segment_tb.vhd(80): VHDL Compiler exiting

so apparently my array cannot be iddentified and i fail to understand why is that the case

You don't appear to have a declaration for a type or subtype in the subtype indication for constant TableArray. An object declaration doesn't accept an array definition, which can only appear in a type declaration which should be visible at the beginning of the constant declaration. ChatGPT is not authoritative on VHDL while the IEEE standard is. You could also search on Stackoverflow for examples of array constants. This is a syntax error where using Modelsim's Verror tool can display the meaning of vcom-1136. — user16145658
– user16145658, Commented May 14, 2024 at 0:54
vcom Message # 1136: "The specified name was referenced but was not found. This indicates that either the name specified does not exist or is not visible at this point in the code." This error reflects the method used to parse and the message is confusing as it does not point to the right place in a series of tokens where a LA 1 parser would note the reserved word array is unexpected and report that. — user16145658
– user16145658, Commented May 14, 2024 at 1:09
For IEEE Std 1076-2002 4.3.1.1 Constant declarations the syntax is "constant_declaration ::= constant identifier_list : subtype_indication [ := expression ] ;" where 4.2 Subtype declarations "subtype_indication ::= [ resolution_function_name ] type_mark [ constraint ]" and "type_mark ::= type_name | subtype_name". No reserved word (array) can be the name of the type or subtype. and 4.1 Type declaration "full_type_declaration ::= type identifier is type_definition ; and 3.2 Composite types, 3.2.1 Array types describes the syntax for array definitions which you used. — user16145658
– user16145658, Commented May 14, 2024 at 1:27
The probability that your beginner's VHDL source code (especially if assisted by AIs) is correct and a widely used tool has an error is very near to zero, comparable with the win of the lottery. — the busybee
– the busybee, Commented May 14, 2024 at 6:06

Jim Lewis · Accepted Answer · 2024-05-14 00:45:03Z

2

You need to create a type first:

type TableArrayType is array (0 to 15) of STD_LOGIC_VECTOR (3 downto 0) ; 

constant  TableArray : TableArrayType := (
        "0000", "0001", "0010", "0011",
        "0100", "0101", "0110", "0111",
        "1000", "1001", "1010", "1011",
        "1100", "1101", "1110", "1111" );

answered May 14, 2024 at 0:45

Jim Lewis

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2 Comments

user16145658 Over a year ago

In other words contrary to the title of the question's assertion the syntax was incorrect?

Jim Lewis Over a year ago

@user16145658 Exactly. I try to identify the issue and then address that I don't get too hung up on the fact that a confused person is challenged to write a good problem statement for an issue that they don't understand.

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