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I'm a junior Electronic Engineering student currently learning Verilog. I've been studying various modeling methods in Verilog, including Structural, Dataflow, and Behavioral modeling. I have a question regarding the conversion of Behavioral modeling to Structural modeling:

Does Verilog automatically convert Behavioral modeling into Structural modeling during synthesis, or do I need to convert the code manually?

I've found a helpful answer on how to convert Behavioral modeling into Structural modeling in Verilog here: Verilog Behavioral (RTL) to Structural. verilog behavioral RTL to structural

However, my main concern is whether this conversion needs to be done manually by me, or if the synthesis tools handle it automatically.

So far, I've written model and testbench code for FSMs, synchronous and asynchronous counters, and registers using Behavioral modeling. My questions might stem from my current level of understanding.

Any insights or resources on how to approach this conversion process and better understand hardware realization would be greatly appreciated.

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Logic synthesis:

In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a computer program called a synthesis tool.

Yes, a synthesis tool reads in the behavioral Verilog code (known as RTL), and outputs a Verilog structural model (also known as a gate-level netlist), when configured to do so.

Refer to the documentation for your specific synthesis tool for more details.

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Thanks! I haven't heard about netlist before, so your answer is really helpful for me.
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The answer from toolic provides the gist of it.

My other answer provides more details about this process for RTL synthesis, by converting behavioral models of digital HDLs (e.g., Verilog, VHDL, SystemVerilog, SystemC, and Chisel HDL) to a tuple/pair of control flow graph and dataflow graph (CFG, DFG), or its hybrid control/data flow graph (CDFG). In turn, non-terminal vertices/nodes in the DFG are operators/operations associated with the arithmetic and logic unit, like adders and multipliers. These are mapped onto appropriate logic blocks/circuits for these operators, such as adders and multipliers. Similarly, the CFG is mapped into a finite state machine, and consequently implemented as a (synchronous) sequential circuit. Structural models of digital HDLs can adequately map these combinational circuits in the DFG and sequential circuit in the CFG.

Reference: https://stackoverflow.com/a/79284832/1531728

However, I would prefer to use the term RTL synthesis to describe the transformation from synthesizable behavioral/RTL Verilog models into structural Verilog models at the gate/logic level.

Traditionally, logic synthesis references to sequential circuit optimization of the finite state machine models (applicable only for sequential circuit models), followed by logic optimization of the combinational circuit (including combinational circuits used to realize sequential circuits).

Reference: https://en.wikipedia.org/wiki/Logic_synthesis

The output of logic synthesis is a cell-level (or gate-level) netlist, hierarchical or otherwise, captured as a "structural model" of digital HDLs to represent a digital circuit/system.

HDLs to model electrical circuits as well as analog, mixed-signal, or radio-frequency (AMS/RF) circuits are: SPICE-like languages; Verilog-A for analog and RF circuits; and Verilog-AMS, VHDL-AMS, and SystemC-AMS for AMS/RF circuits. There are electronic design automation (EDA) software to map behavioral AMS/RF circuit models into transistor/component/element -level netlists, and EDA software to provide macromodels of transistor/component/element -level netlists as behavioral models.

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