I have a very simple module that waits for the valid signal to become 1 and then sets the data signal to 1 as below:
module test2(
input clk,
input valid,
output reg data = 0
);
always @(posedge clk) begin
if(valid) begin
data <= 1;
end
end
endmodule
The problem is with my testbench. When I use the following testbench, the result is weird:
module test( );
reg clk = 1;
reg valid = 0;
wire data;
always
clk = #5 ~clk;
initial begin
@(posedge clk);
@(posedge clk);
@(posedge clk);
valid = 1;
end
test2 uut(
.clk(clk),
.valid(valid),
.data(data)
);
endmodule
This leads to the following result:
As is obvious, the data signal and valid signal have changed their value at the same time (same posedge clk). Since we declared our design module sequentially, it should make a flipflop, but the result is not as flipflop behavior.
Furthermore, if I change the line valid = 1; to valid <= 1; in my testbench, the output is modified:
What is the problem here, and why does blocking or nonblocking assignment in the initial block in the testbench affect the design behavior?
I am using Vivado2023 for simulation.
