Verilog counter delay in task not working

Question

I'm trying to generate different delays in multiple places using task WAIT in a synthesizable module, and the code is as follows:

 module LCD
  (
    input          clk,
   output         en
 
  );  
     reg [ 15 : 0 ] delay = 0;         //  counter for state machine
     reg [ 15 : 0 ] COUNT= 0;          // counter  for "WAIT"
    
     always @ (posedge clk_lcd) begin
     
          COUNT = COUNT + 1'b1;        // COUNTER FOR TASK "WAIT"
                           .
          delay = 2000;
          WAIT(en, delay);             // call task
               .
          delay = 500;
          WAIT(en, delay);             // call task
     end                               // always end
               .                    
     
     task automatic WAIT               // task to wait till delay time is up
     (     
       output EN,
       input [ 15 : 0 ] DELAY
      );
    begin                              
       COUNT = 0;
       if(COUNT == DELAY)begin         // create delay using counter                                                
          EN = 0;                                                        
          COUNT = 0;
       end else begin    
          EN = 1;                                                        
          COUNT = COUNT + 1'b1;  
       end                                        
    end
    endtask                            //  end task
  endmodule

But, they don't work. I'm a learner; please help.

Please clarify your specific problem or provide additional details to highlight exactly what you need. As it's currently written, it's hard to tell exactly what you're asking. — Community
– Community Bot, Commented Dec 4, 2023 at 4:55

toolic · Accepted Answer · 2023-12-04 11:42:41Z

Since you are new to Verilog, here is a quick start to learn about synthesizable constructs. It is not common to use a task for synthesizable code; they are much more common for non-synthesizable testbench code.

As I'm sure you have already discovered if you tried to simulate or synthesize your code, the code has several syntax errors. This requires a new approach. Generally, a counter can be coded with a simple always block, and there is no need for a task. Instead of writing code to sequentially load the counter with 2 delay values like that, use a state variable to keep track of the delay. Here is a common way to code up a counter:

module LCD (
    input clk,
    input reset,
    output reg en
);  
    reg state;
    reg  [15:0] COUNT;
    wire [15:0] DELAY = (state) ? 500 : 2000;
    
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            COUNT <= 0;
            state <= 0;
            en <= 0;
        end else if (COUNT == DELAY) begin
            COUNT <= 0;
            state <= ~state;
            en <= 1;
        end else begin
            COUNT <= COUNT + 1'b1;
            en <= 0;
        end
    end
endmodule

The enable is a pulse that goes high for 1 cycle every time the counter reaches the delay value. This should get you moving in the right direction.

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