how to compare an integer and an std_logic vector

Question

I have an array of signals. I want to write to the appropriate cell in the array when a signal which is the "selector" is equal to the cells number. To save on writing and code lines I generate the assignment in a generate loop:

read_data_signals_gen: for i in 0 to (CAU_num -1) generate

    v_direction_sig(i)(0) <=  DATA_IN when (chosen_flow_sig = i) and (read_state = st_read_v_direction_0) else
                              v_direction_sig(i)(0);
    v_direction_sig(i)(1) <=  DATA_IN when (chosen_flow_sig = i) and (read_state = st_read_v_direction_1) else
                              v_direction_sig(i)(1);
    v_direction_sig(i)(2) <=  DATA_IN when (chosen_flow_sig = i) and (read_state = st_read_v_direction_2) else
                              v_direction_sig(i)
  ...
end generation read_data_signals_gen;

chosen_flow_sig is an std_logic_vector (1 downto 0) and gets "00", "01", "10" or "11" to denote the number of the cell, And CAU_num is an integer constant equal to 4. How do I create the comparison inside the when statement so that an integer number will be equal to its binary translation?

And a related question. Is there a way to perform the following code:

type  BitArray is array (natural range <>) of std_logic;

sel_sig : std_logic_vector(0 to 1);
bit_arr : BitArray(0 to 3)

sel_sig <= "00"
bit_arr(sel_sig) <= '1'  -- HOW TO PERFORM THIS?

kheyse · Accepted Answer · 2012-11-05 11:40:09Z

5

You are probably looking for

to_integer(unsigned(sel_sig))

e.g.

bit_arr(to_integer(unsigned(sel_sig))) <= '1'

or

if to_integer(unsigned(sel_sig))=12 then ...

answered Nov 5, 2012 at 11:40

kheyse

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2 Comments

SIMEL Over a year ago

Can I use it in a comparison?

kheyse Over a year ago

You can use it as a regular integer, also in a comparison.

Martin Thompson · Accepted Answer · 2012-11-05 15:03:53Z

2

If chosen_flow_sig represents a number, use a numerical type for it (unsigned or integer for example). If you use std_logic_vector you're giving yourself pain that you don't need!

http://parallelpoints.com/node/3

answered Nov 5, 2012 at 15:03

Martin Thompson

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4 Comments

SIMEL Over a year ago

chosen_flow_sig is created by a component I made (It a logic implementation of my selection algorithm). Can a component return an integer?

Martin Thompson Over a year ago

Yes, you can have whatever types you like on the ports of an entity. It even synthesises :)

Sylvain Huard Over a year ago

Martin, Thanks very much for that link. It explains and solves a pletora of frustrations I've had for a long time. I changed my coding style accordingly. Code is cleaner easier to read.

Martin Thompson Over a year ago

Thanks Sylvain - glad to be of service :)

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