Comparing integer and binary in VHDL

Here is a simple test comparing regs to integers:

module test;

reg        [9:0]   val;
reg signed [9:0]   sval;


initial begin
  #1ns;

  val = 10'd1;
  #1 $display("is it equal %b", val == 1);
  val = 10'd2;
  #1 $display("is it equal %b", val == 2);
  val = 10'd3;
  #1 $display("is it equal %b", val == 3);

  //Signed
  val = -10'd1;
  #1 $display("is it equal %b", val == -1);
  val = -10'd2;
  #1 $display("is it equal %b", val == -2);
  val = -10'd3;
  #1 $display("is it equal %b", val == -3);

  // Using Signed register
  sval = -10'd1;
  #1 $display("is it equal %b", sval == -1);
  sval = -10'd2;
  #1 $display("is it equal %b", sval == -2);
  sval = -10'd3;
  #1 $display("is it equal %b", sval == -3);
end
endmodule

Gives me:

is it equal 1
is it equal 1
is it equal 1
is it equal 0
is it equal 0
is it equal 0
is it equal 1
is it equal 1
is it equal 1

For me the positive numbers work fine but fails with negative values. You have to declare the reg as signed. For the comparison to work. With that in mind you should be able to compare reg to integer.

From your mention of std_logic_vector, I assume you are actually working in VHDL, not Verilog.

If your vectors represent numbers, use the unsigned or signed types from ieee.numeric_std, instead of vectors. Then you can compare directly with integers.

If you insist on using std_logic vector, then convert it before:

 if unsigned(some_vector) < some_integer then

You can compare. The difference between integer and reg is that reg by default is an unsigned type single bit value; whereas integer is signed type 32 bit value. Make sure that o_reminder and reminder are of same type i.e, both are either signed or unsigned. same case with the o_quotient and quotient.

I don't see any issue if you have declared as below.

integer o_reminder, o_quotient;
reg signed [31:0] reminder,quotient;

or

integer unsigned o_reminder, o_quotient;
reg [31:0] reminder,quotient;