Some body suggest me how to get the instantiation name without "." like "genblk1.name" if i use generate for loop for creating more module instantiations.
I want instantiation names like addr_1,addr_2 (addr my module name)
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You are meant to show what you have tried? otherwise you will likely get down/close votes.Morgan– Morgan2014-08-27 11:35:12 +00:00Commented Aug 27, 2014 at 11:35
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1Can you explain what the problem is with having a "." in the path name, other than it doesn;t look nice to you?dave_59– dave_592014-08-27 13:32:38 +00:00Commented Aug 27, 2014 at 13:32
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we would like to tap few signals of DUT for monitoring in DUT, for some special cases. So it is easy to engineer just go by a instantiation name.Narasimha– Narasimha2015-06-30 11:17:25 +00:00Commented Jun 30, 2015 at 11:17
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2 Answers
You'll always get a "." when you instantiate modules inside generate blocks. This is because every generate block creates a new level of hierarchy. The first string is the name of the generate block, while the second is the name of the instance. The only thing you can do is control the name of the generate block:
module some_module;
endmodule // some_module
module top;
parameter a = 1;
if (a) begin : if_gen_block
some_module inst();
end
genvar i;
for (i = 0; i < 5; i++) begin : loop_gen_block
some_module inst();
end
endmodule // top
The if generate block will create "if_gen_block.inst", whereas the for gen block will create 'loop_gen_block[0].inst', 'loop_gen_block[1].inst', etc. This behavior is specified in the SystemVerilog LRM.
Comments
If you declare an object inside a generate block, ordinarily the name of that object is hierarchical, i.e., loop_gen_block[0].object, it may or may not need to be escaped, i.e., \loop_gen_block[0]
If you don't name the gen block, the compiler will. Might be genblock0, might be genblock[0]. Note that the index is only meaningful within generate; it's not an array.
For a generate loop, objects declared inside the loop must be referenced hierarchically to disambiguate them.
For an if generate, in Vivado at least, you can specify -noname_unnamed_generate to xelab, and if there's no ambiguity, an object declared in the block can be referenced without the added hierarchical level, which can be very useful.
Just my experience; don't flame me if I got something wrong.
