6-bit binary counter with LED output shows X

Question

I can't understand why my program returns nothing. I'm trying to make a simple 6-bit up-counter that counts on a button press.

module top (CLK, BTN_RST, LED, BTN_C);
    input CLK, BTN_RST, BTN_C;
    output [5:0]LED;
    reg [5:0]LED;
    always @(posedge CLK or posedge BTN_RST) begin
         if (BTN_RST) begin
              LED <= 6'b000000;
           end
         else begin: COUNT           
              while (BTN_C) begin
                    LED <= LED + 1'b1;
                    disable COUNT;
              end
            end
    end
endmodule

The testbench is:

module top_test;
    reg CLK;
    reg BTN_RST;
    reg BTN_C;
    reg [5:0]LED;

    initial begin
        CLK = 0;
        BTN_RST = 0;
        BTN_C = 0;
        #1 BTN_RST = 1;
        #5 BTN_RST = 0;
        #10 BTN_C = 1;
        #50;
    end
   
    always
    begin
    #5 CLK=~CLK;
    end
endmodule

This code compiles and runs (as I can see on iSim), but the LED output gives me XXXXXX. I think I'm not only got some mistakes here, but I also can't understand how the testbench works and how to make right assignments on input and output. Can anyone please help me?

toolic · Accepted Answer · 2020-10-10 18:12:58Z

You need to add an instance of your design in your testbench. Now, LED is no longer X; I see it counting up from 0.

module top_test;
    reg CLK;
    reg BTN_RST;
    reg BTN_C;
    wire [5:0]LED;

    initial begin
        CLK = 0;
        BTN_RST = 0;
        BTN_C = 0;
        #1 BTN_RST = 1;
        #5 BTN_RST = 0;
        #10 BTN_C = 1;
        #50;
    end

    always
    begin
    #5 CLK=~CLK;
    end

top dut (
        // Inputs:
    .BTN_C    (BTN_C),
    .BTN_RST  (BTN_RST),
    .CLK      (CLK),
        // Outputs:
    .LED      (LED)
);

endmodule

I changed reg to wire for LED in top_test. I see LED increasing from 0 when I use VCS as a simulator. But, when I switch to Incisive, LED stays at 0.

I think your while/disable code is causing a problem. I have recoded it to look a little more standard:

module top (CLK, BTN_RST, LED, BTN_C);
    input CLK, BTN_RST, BTN_C; //
    output [5:0]LED;
    reg [5:0]LED;
    always @(posedge CLK or posedge BTN_RST) begin
        if (BTN_RST) begin
            LED <= 6'b000000;
        end else if (BTN_C) begin           
            LED <= LED + 1'b1;
        end
    end
endmodule

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