creating an ALU in verilog

Question

I was wondering if it were possible to have if statements, so for the ALU I am trying to build. I am passing values from a datapath test bench to a datapath, from the datapath into the ALU, and from the ALU back to the datapath. I am trying to create a control unit which will only pass values through a certain component if the corresponding control_ALU is activated.

Here is my verilog code :

module ALU (
  input en_ALU, clk_ALU,
  input [31:0]  inputA, inputB, control_ALU,
  output [31:0] resultc
);
wire [31:0] res_out;

always @(control_ALU)
begin       
  if(control_ALU[1])    begin       
    andLogic  andLogic_component(
      .dataA (inputA),
      .dataB (inputB) ,
      .resultA (res_out)
    );
  end
  if(control_ALU[2])    begin
    negate m0(
      .inputnegate  (inputA), 
      .resultnegate (res_out)
    );
  end   
end 

reg64bit z(
  .clk(clk_ALU) ,
  .clr(clr),
  .enable(en_ALU),
  .inputd(res_out),
  .outputq(resultc)
);      

endmodule

"which will only pass values through a certain component if the corresponding control_ALU is activated", No, you must always drive signals or tri-state them. A module instance is a representation of hardware, it can not be created or destroyed on the fly, as would be implied by having an instance inside an if. — Morgan
– Morgan, Commented Feb 25, 2015 at 11:04

Greg · Accepted Answer · 2015-02-25 16:13:53Z

1

Not sure you can put the instance in IF statement.

But I know you can declare your instance first, then give each of them a different output name, then use CASE statement or IF statement to select different output as your top module ALU output.

case(funct)

3'b000: //ALU control signal
ALU_out = add;

3'b001: 
ALU_out = sub;

3'b010:
ALU_out = andlogic;

 ...
 ...
 ...

endcase

Remember to give a default if the case statement is not complete.

Hope this is helpful. :-)

edited Feb 25, 2015 at 16:13

Greg

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answered Feb 25, 2015 at 16:11

Shuaiyu Jiang

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