How can I use Verilog defines in an if-else statements

Question

I have a Verilog define like this:

`define NUM_BANKS 4

and if want to use it in the following code:

if (`NUM_BANKS > 1)
  do something ..
else
  do something else ..

Lint tool is complaining that this expression is going to always be evaluated to true.

wilcroft · Accepted Answer · 2015-03-27 02:25:21Z

1

After the `define is applied, the if will always evaulate 4 > 1. The compiler is giving an error, since the if will always be irrelevant.

I'd recommend either replacing your `define with a parameter (if you're looking to have it be changed by a higher-level module or instantiation), or use the compiler directives (http://www.csee.umbc.edu/portal/help/VHDL/verilog/compiler.html for example)

`define HASBANKS
`ifdef (HASBANKS)
...
`else
...
`endif

answered Mar 27, 2015 at 2:25

wilcroft

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1 Comment

mshaaban Over a year ago

Thanks Wilcroft, that's actually what I did to make it work. I typecasted the define into a parameter and then used the parameter in the if statement.

Neo Song · Accepted Answer · 2015-03-27 02:05:48Z

0

Lint is correct, since in your expression, 4 > 1 is always true. So if this is what you want, there is no problem.

Neo

answered Mar 27, 2015 at 2:05

Neo Song

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