Syntax error: matching begin/end

Question

module booth(num1,num2,prod);

input [22:0] num1,num2;
output [45:0] prod;
reg [22:0]num1_bar;
reg [46:0]sub_1;
reg [22:0]temp;
reg [22:0]result;
reg [1:0]sel;
reg [22:0]add;
reg [22:0]zeros;

assign temp = ~ num1;
assign num1_bar = temp + "00000000000000000000001";
assign sub_1 = {zeros[22:0], num2, "0"};

integer i;
always @* begin
    for( i = 0; i < 22; i = i+1) begin
        assign sel = sub_1[1:0];
        if(sel == "10") begin
            assign add = sub_1[46:24] + num1_bar;
            assign sub_1 ={add[22],add,sub_1[23:1]};
        end
        elseif(sel == "01") begin
            assign add = sub_1[46:24] + num1 ;
            assign sub_1 ={add[22],add,sub_1[23:1]};
        end
        else begin
            assign sub_1= {sub_1[46] ,sub_1[46:1]};
        end
    end

endmodule

I am trying to implement a floating point multiplier using carry look ahead adder and booth multiplier. After running the above code following errors has occurred only for the booth multiplier. Please help me out.

ERRORS:

Summary Tue Apr 7 15:25:28 2015

Summary New ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 45. Syntax error near "begin". ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 49. Syntax error near "else". ERROR ProjectMgmt:806 - "D:/XILINX PROGRAM/bth/booth.v" Line 54. Syntax error near "endmodule". INFO ProjectMgmt:1845 - Analyzing Verilog file "D:/XILINX PROGRAM/bth/booth.v" into library work

mcleod_ideafix · Accepted Answer · 2015-04-07 12:11:34Z

0

You seem to have a confusion between VHDL and Verilog.

Vector constants in Verilog are in the form: Y'zXXXXXXX where Y is the number of bits of the vector, z is the base (b for binary, d for decimal, h for hexadecimal), and XXXX is the constante value in the specified base.
else if must separated

For example, the line:

if(sel == "10") begin

Must be rewritten as:

if(sel == 2'b10) begin

For large vectors, you can ommit the size specifier, and write the constant as this:

assign num1_bar = temp + 'b00000000000000000000001;

answered Apr 7, 2015 at 12:11

mcleod_ideafix

11.5k2 gold badges30 silver badges33 bronze badges

Sign up to request clarification or add additional context in comments.

2 Comments

Greg Over a year ago

Large vectors should have the size specified, many simulators will infer 32 as the width if it not explicit. For this large vectors it is easier and more precise to write 23'b01. assign should not be used inside an always block; the feature is being scheduled for depreciation.

Learner Over a year ago

I have rewritten the code for the booth multiplier but again there is some error in the last blocking assignment (prod = result) .Please help me sir .

mkrieger1 · Accepted Answer · 2015-04-07 12:18:52Z

0

You are missing an end matching the begin of the always block.

(Once you have fixed that, you will see that there are other errors, too. See mcleod_ideafix's answer.)

edited Apr 7, 2015 at 12:18

answered Apr 7, 2015 at 12:07

mkrieger1

24.2k7 gold badges68 silver badges84 bronze badges

2 Comments

Learner Over a year ago

Can please tell me where and how to use the 'always ' block in my code ?

mkrieger1 Over a year ago

You already have an always block: always @* begin ..., what is missing is one more end, right before endmodule.

Collectives™ on Stack Overflow

Syntax error: matching begin/end

2 Answers 2

2 Comments

2 Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

2 Answers 2

2 Comments

2 Comments

Your Answer

Sign up or log in

Post as a guest

Related