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I have a very long std_logic_vector of size 752. Every 8 bits in this vector needs to be reversed for a function. So

a(0) <= b(7)
a(1) <= b(6)
a(2) <= b(5)
a(3) <= b(4)
a(4) <= b(3)
a(5) <= b(2)
a(6) <= b(1)
a(7) <= b(0)

And then reversing it for the next 8 bits

a(8) <= b(15)
a(9) <= b(14)
a(10) <= b(13)
a(11) <= b(12)
a(12) <= b(11)
a(13) <= b(10)
a(14) <= b(9)
a(15) <= b(8)

And this just goes on like this for every 8 bits till 752. Is there a better way to do this? I was thinking of using a for loop within a for loop. The first loop is used for checking whether the element if a divisible by multiples of 8-1 , and the second for loop is for reversing the values every 8 bits.

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  • 2
    The double loop should work. Commented Oct 24, 2015 at 9:07
  • @BrianDrummond do you think this would take too much resources on the FPGA with such a double loop? Commented Oct 24, 2015 at 9:09
  • Tell me what you find, And compare it with a double "for ... generate" outside a process. Commented Oct 24, 2015 at 9:14
  • 4
    @holyprinter: In the FPGA it is just wire renaming that is resolved at compile time, so it won't take any resources in the FPGA. Commented Oct 24, 2015 at 10:19
  • While these assignments don't consume logic resources how do you simulate efficiently? 752 concurrent assignment statements mean 752 processes post elaboration each with a sequential assignment, all sensitive to b regardless of whether the value of the a output is affected. You want the number of processes equal to the number of times it takes you to assign all of b each sensitive to a unique signal event. Your code isn't a Minimal, Complete, and Verifiable example for solving that. Big things can eat simulation resources. Commented Oct 24, 2015 at 21:01

1 Answer 1

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One solution would be to split the input into chunks of 8 bits and do the reverse only within each chunk:

process(b)
begin
  for chunk in 0 to (752/8)-1 loop
    for i in 0 to 7 loop
      a(8*chunk+i) <= b(8*chunk+(7-i));
    end loop;
  end loop;
end process;
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