How do you manipulate input arrays in an always block (verilog)?

Question

I'm very new to verilog and i'm just starting to understand how it works. I want to manipulate an input to a module mant[22:0], in an always block but I am not sure how to go about it.

module normalize(mant,exp,mant_norm,exp_norm);

    input [22:0]mant;
    input [7:0]exp;

    output [22:0]mant_norm;
    output [7:0]exp_norm;

    reg mantreg[22:0];
    reg count=0;

    always@(mant or exp)
    begin

    mantreg<=mant; //this gives an error
        if(mant[22]==0)
        begin

          mant<={mant[21:0],1'b0};//this also gives an error
          count<=count+1;

        end 
    end
endmodule

so i have to shift the mant register if the bit22 is zero and count the number of shifts. I am so confused about when to use reg and when to use wire and how to do the manipulation. please help let me know how to go about it.

@TocToc Of course you can use a shift operator for shifting in Verilog, but it is also very common to use a concatenation operator as the questioner has done. So, the question is in no way a duplicate of the question you cite. I haven't been here long, but this sort of thing seems to happen all the time: more experienced users are very quick to jump on alleged duplicates, but don't really seem to care whether the supposed duplicate actually answers the original question and hence is useful to the questioner. The hypothetical future questioner seems to take priority over the current questioner. — Matthew
– Matthew, Commented May 25, 2016 at 15:34
@MatthewTaylor: indeed, I have been quick on this one, I apologies... — TocToc
– TocToc, Commented May 26, 2016 at 14:55

Dhaval Patel · Accepted Answer · 2016-05-25 15:09:55Z

1

As you can see in your code you are assigning vector value (mant) to array of 23(mantreg). Instead you should declare mantreg as reg [22:0] mantreg (which is vector of 23 bit).

Wire type variable can not be assigned procedurally. They are used only in continues assignment. Other way around reg varible can only be procedural assigned.

For that try to read out LRM of Verilog .

answered May 25, 2016 at 15:09

Dhaval Patel

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