How to read a bit file in VHDL?

Question

I am new to VHDL. I am doing a MP3 decoder using VHDL and i happen to come across with this huffman coding from a website. However, I have difficulty in figuring out which lines actually indicates the input bit file. Below is the source code:

use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.all_types.all;         
use work.huffman_types.all;  -- this file contains all the tables of huffman decoders

entity huffman is
port( clk   : in  std_logic;      -- input clock signal
      rst   : in  std_logic;      -- reset signal ('1' = reset)
      start : in  std_logic;      -- start='1' means that this component is activated
      done  : out std_logic;      -- produce a done signal when process is finished
      gr    : in  std_logic;      -- granule ('0'=granule0, '1'=granule1)
      bin   : in  std_logic_vector(7 downto 0);    -- input main data for huffman
      addr  : out std_logic_vector(9 downto 0);    -- address for main data
      dout  :  out std_logic_vector(31 downto 0);   -- data to memory
      memc  : out mem_control_type;  -- memeory controll signal
      sco   : out scalefac_type;  -- output scale factors 
      frm   : in  frame_type      -- contains all header and side information for the current frame
  );
end;

architecture behavioral of huffman is
type state_type is 
(IDLE1,IDLE2,IDLE3,READ,READ1,READ2,READREADY,SCALE,HUFFMAN,HUFFBIGVALUE,TABLELOOKUP1,HUFFCOUNT1,TABLELOOKUP2,HUFFEND,DATAREADY,READY );
signal cs,ns:state_type;
type is_type is array (0 to 575) of integer;
signal isg : is_type;
signal addrcount1:std_logic_vector(9 downto 0);
signal valuebuffer : std_logic_vector(0 to 8191 );

begin

process(cs, frm, gr, start)

variable scalefac : integer;
variable count : integer ;
variable memaddrcount : std_logic_vector(9 downto 0);
variable scout : scalefac_type;
variable bitpos:std_logic_vector(12 downto 0);
variable region1start,region2start,bigvalues,count1s,start_bit1,start_bit2,start_bit,tempbit: integer;
variable line,line1,region,old_region : integer;
variable u,w,x,y,linbits:integer;
variable level,level1,value,temp,templevel:integer;
variable tindex:integer range 0 to 33;
variable tempvector : std_logic_vector(7 downto 0);
variable tempvector1 : std_logic_vector(3 downto 0);
variable slenval0,slenval1:integer;
variable tempval,tempdata,temphuff,temphuff1,temppos:integer;
variable tempcount1:std_logic;

begin

case cs is
  when IDLE1   =>  
                   addrcount1 <= (others =>'0');
           ns<=IDLE2;
  when IDLE2   =>  
                   done <= '0';
                   count :=0;
           line :=0;
           line1 :=0;
           bigvalues:=0;
           count1s:=0;
           start_bit:=0;
           linbits:=0;
           tempvector1:=(others =>'0');
           tempvector:=(others =>'0');
           tindex:=0;
           temp:=0;
           value:=0;
           isg<=(others=>0);   
               ns<=IDLE3;
  when IDLE3  => 
                 if (start = '1') then
             memaddrcount :=(others =>'0');
                 end if;
                 ns<=READ;
  when READ   => 

                 addr <= addrcount1;
                 ns<=READ1;

  when READ1=>
        ns<=READREADY;

  when READREADY => 
            valuebuffer(count to count+7 ) <= bin;
            count := count +8;
                addrcount1 <= addrcount1 +1;

                    if count=8192 then
                       if gr='0' then
              bitpos:=conv_std_logic_vector((conv_integer(frm.sideinfo.main_data)*8),13);
                   else
                  start_bit2:=conv_integer(bitpos);
                       end if;
                          ns<= SCALE;
                    else
                        ns<= READ;
                    end if;
                    .
                    .
                    .

As we can see, this line is the input main data

bin   : in  std_logic_vector(7 downto 0);    -- input main data for huffman

Is this line indicates the bit file is fed into the buffer?

valuebuffer(count to count+7 ) <= bin;

I wonder why the read_mode method is not used. If read_mode is needed, where should it be inserted?

There is no file anywhere in this code. bin is a single byte input. — user1818839
– user1818839, Commented Nov 15, 2016 at 17:16
@BrianDrummond, thanks for clarifying. I have a binary file which is converted from .mp3 format. How should I modify the code so that it can read the bit file? — Cyan
– Cyan, Commented Nov 15, 2016 at 17:22
How should I modify the code so that it can read the bit file? is too broad for this venue. Hardware doesn't generally have a file system without a processor. Are you asking how to load a file into the (not shown) memory? The OpenCores project MP3 decoder has a readme file which describes what huffman.vhd does. There's FPGA-BASED ARCHITECTURE OF MP3 DECODING CORE FOR MULTIMEDIA SYSTEMS can be helpful in understanding the code shown (see Fig .19). — user1155120
– user1155120, Commented Nov 15, 2016 at 18:05
Looking at the huffman.vhd file the state machine in the non-clocked process is full of inferred latches and combinatorial loops. None of the counters in the process are clocked (addrcount1, memaddrcount, count, count1s). Inferred latches occur when there aren't assignments when a both a particular condition assigning something is true and not true. Similar flaws in other files. It's a safe bet there'd be significant work involved in producing something synthesis eligible. This matches the project status on OpenCores. — user1155120
– user1155120, Commented Nov 16, 2016 at 0:23

Fisher · Accepted Answer · 2016-11-18 16:30:02Z

2

Normally only read a file in testbench.

process
  variable status_input  : file_open_status;
begin
  -- Open files
  file_open(status_input, file_input, "../your_text_file.txt", read_mode); ...

After read the content of the file, you can feed the data to a module's I/O.

The code you posted is terrible. Lots of issues, I'll never reference it.

answered Nov 18, 2016 at 16:30

Fisher

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2 Comments

Cyan Over a year ago

Thanks @Fisher. Are you working on the same project (MP3 decoder using VHDL)?

Fisher Over a year ago

@ Cyan I'm using VHDL, but different project.

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