I have an 8-bit signed variable A and a 3-bit value n. I want to shift operator n times in an always statement but it doesn't work and output is x.
reg signed [7:0] A = //something;
reg [2:0] n = 3'b//something
always @(A, n) begin
w = 8'b0;
w = A >> n;
So what type of variable shift operator needs? and how can i convert n to that type?
The type of the arguments is not the problem that you are having. The problem is that the always block is not getting run. The values of A and n are not changing and so the always @ is not ever getting run. If this was a real program you wouldn't have a problem since those signals would be driven from somewhere and propagate to this block. In any case, any integral value is fine for n, you just need to have it change during the simulation. To see that it was never run you could use a $display within the always block and you'll see when it runs.
When I run the following:
module test;
reg signed [7:0] A = 'h17;
reg [2:0] n = 3'b010;
reg signed [7:0] w;
always @(A, n) begin
w = A >> n;
$display("%0t: always has been run", $time);
end
initial $monitor("%X %d %X", A, n, w);
endmodule
Output:
17 2 xx
If instead I use the following code, then I get the expected response:
module test;
reg signed [7:0] A;
reg [2:0] n;
reg signed [7:0] w;
initial begin
#10;
A = 'h17;
n = 3'b010;
end
always @(A, n) begin
w = A >> n;
$display("%0t: always has been run", $time);
end
initial $monitor("%X %d %X", A, n, w);
endmodule
Output:
xx x xx
10: always has been run
17 2 05
The other option is that if you have a SystemVerilog simulator, then you can just use always_comb which unlike the always @ it will execute without changes on the inputs at time 0.
For shift operator needs an integer type.
To convert to integer you can use int'(n)
Or you can declare integer type signal and assign to it, like
reg signed [7:0] A = ;//something;
reg [2:0] n = 3'b;//something
integer n_int;
always @(A, n) begin
n_int = n;
w = 8'b0;
w = A >> n_int;
