I'm trying to learn verilog, and I don't understand what is wrong when using the for loop.
In the example module I'm trying to implement, I'm going to set the first bit of the output based on the inputs, while the remaining bits of the output are going to be set based on both the input, and the previous bit of the output-
module example_module(A,B,C);
input [15:0] A;
input [15:0] B;
output [15:0] C;
reg[15:0] C;
integer i;
always@(A or B)begin
C[0] = A[0]&B[0];
for(i = 0;i<15;i=i+1)begin
C[i+1] = A[i+1]|(B[i+1]&C[i]) ;
end
end
endmodule
For the testbench-
`timescale 1ns/1ns
module example_module_tb;
reg[15:0] A;
reg[15:0] B;
wire [15:0] C;
example_module e(A,B,C);
initial begin
A = 16'd23;
B = 16'd32;
end
initial begin
$dumpfile("example_module_tb.vcd");
$dumpvars;
end
initial #400 $finish;
endmodule
When I run this on veriwell, and then use GTK wave, I get the output wire C to be 16'bxxxxxxxxxxxxxxx0, basically the first bit is set, but the others are not?
Could someone please explain how to fix this?
Thanks!
EDIT: Here are the actual 3 files I'm using, but I'm getting xxx for the CLA_logic_tb.v!
GP_generator.v
module GP_generator(A,B,G,P);
input [15:0] A;
input [15:0] B;
output [15:0] G;
output [15:0] P;
reg [15:0] G;
reg [15:0] P;
integer i;
always@(A or B)
begin
for(i = 0; i<16; i= i +1)begin
G[i] = A[i]&B[i];
P[i] = A[i]^B[i];
end
end
endmodule
CLA_logic.v
module CLA_logic(A,B,C);
input [15:0] A;
input [15:0] B;
output [15:0] C;
reg[15:0] C;
wire [15:0] G;
wire[15:0] P;
GP_generator g1(A,B,G,P);
integer i;
always@(A or B)begin
C[0] = A[0]&B[0];
for(i = 0;i<15;i=i+1)begin
C[i+1] = G[i]|(P[i]&C[i]) ;
end
end
endmodule
CLA_logic_tb.v
`timescale 1ns/1ns
module CLA_logic_tb;
reg[15:0] A;
reg[15:0] B;
wire [15:0] C;
CLA_logic c(A,B,C);
initial begin
A = 16'd23;
B = 16'd32;
end
initial begin
$dumpfile("CLA_logic_tb.vcd");
$dumpvars;
end
initial #400 $finish;
endmodule
The first bit of C is set, but the rest give xxx
