VHDL std_logic_vector without range

Question

I'm facing a problem that I cannot solve, so I'm asking for your help. In a VHDL package I should define a customized type of array in the following way, in order to use it as a parameter in the function:

type matrixsignal is array (integer range <>) of std_logic_vector;
function first_defined(matrix:matrixsignal; start_index,col_index:integer) return integer;

As you can see, the std_logic_vector should not have range, since it depends on a variable which is present in the main code. But, of course, the compiler rejects this structure...I read that it is only possible with VHDL2008 but still...is there any kind of possible solution to solve this problem?

Rejects which structure? Perhaps you could provide a minimal reproducible example including a demonstration of the problem as well as specifying whether or not you are using -2008 compatibility? — user1155120
– user1155120, Commented Apr 7, 2018 at 10:50
Yes, it's a VHDL-2008 feature. Are we talking about synthesis code or simulation code? What tool and version are you using? Have you enabled VHDL-2008 in your tool? — Paebbels
– Paebbels, Commented Apr 7, 2018 at 12:23

DonFusili · Accepted Answer · 2018-04-09 08:00:16Z

1

Workaround pre-VHDL2008:

Understand why this doesn't work

Expanding a signal depending on a variable doesn't make sense in hardware, you simply can't add wires depending on a number you have defined somewhere.

So solve it

your variable will have a defined upperbound, something like

constant c_bus_maxwidth : integer := 6;
variable r_bus_usedwidth : integer 0 to c_bus_maxwidth;

If you define this constant high enough in your compilation hierarchy, you can use it to define a subtype of your matrix signal:

type t_matrixsignal is array(integer range<>) of std_logic_vector;
subtype t_definedmatrixsignal is t_matrixsignal(c_bus_maxwidth-1 downto 0);

Now all you need to do is take in a t_definedmatrixsignal to your function and also take in your variable r_bus_usedwidth. Trivial changes to your function code give you the functionality you want. Busses during implementation will always use c_bus_maxwidth std_logic_vectors.

answered Apr 9, 2018 at 8:00

DonFusili

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1 Comment

JHBonarius Over a year ago

"you simply can't add wires depending on a number you have defined somewhere." Well... Yes you can. That's why its included in VHDL-2008 and is perfectly synthesizable, as long as the number is constant at compile time.

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