Unexpected behaviour on this code, what is going on?

Question

module myModule (CLK, A);

input CLK;
output reg [3:0] A = 4'b0000;


reg Sin = 0;

always @(posedge CLK)
begin

//Sin <= ((~A[2]&~A[1]&~A[0])|(A[2]&A[1]));
//A[0] <= A[1];
//A[1] <= A[2];
//A[2] <= A[3];
//A[3] <= Sin;

A <= {(~A[2]&~A[1]&~A[0])|(A[2]&A[1]), A[3], A[2], A[1]};

end


endmodule

When I comment A <= {(~A[2]&~A[1]&~A[0])|(A[2]&A[1]), A[3], A[2], A[1]}; and uncomment the commented part, i.e , replacing them, I cannot get the same working anymore.

module myModule (CLK, A);

input CLK;
output reg [3:0] A = 4'b0000;


reg Sin = 0;

always @(posedge CLK)
begin

Sin <= ((~A[2]&~A[1]&~A[0])|(A[2]&A[1]));
A[0] <= A[1];
A[1] <= A[2];
A[2] <= A[3];
A[3] <= Sin;

//A <= {(~A[2]&~A[1]&~A[0])|(A[2]&A[1]), A[3], A[2], A[1]};

end


endmodule

Is there a functional difference between these two lines of code? They seem equal to me.

A <= {(~A[2]&~A[1]&~A[0])|(A[2]&A[1]), A[3], A[2], A[1]}; is working correctly, while the other one is not correct.

Thanks.

toolic · Accepted Answer · 2020-05-14 19:42:46Z

1

They are different because Sin is a registered version of that expression (delayed by one cycle).

You could use a continuous assignment for Sin to get the same behavior:

module myModule (CLK, A);

input CLK;
output reg [3:0] A = 4'b0000;

wire Sin = (~A[2]&~A[1]&~A[0])|(A[2]&A[1]);

always @(posedge CLK)
begin
    A <= { Sin, A[3], A[2], A[1] };
end

endmodule

answered May 14, 2020 at 19:42

toolic

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Serge · Accepted Answer · 2020-05-14 19:44:45Z

1

there is a small difference in your case which makes both parts behave differently. Non-blocking assignment in Sin <= ((~A[2]&~A[1]&~A[0])|(A[2]&A[1])); will delay its execution till the end of the simulation tick.

As a result, A[3] <= Sin; will not be assigned till the end clock edge. This behavior will mismatch synthesized behavior.

In order to fix it, you need to use blocking assignment to Sin.

Sin = ((~A[2]&~A[1]&~A[0])|(A[2]&A[1]));

This way both parts will be functionally identical.

answered May 14, 2020 at 19:44

Serge

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