Verilog function result different from expected

Question

I'm using this function snippet to make my 7 segment display more readable. Why does it print '00' and not '0E'?

module main;

function disp;
input [6:0] a;
begin
    case (a)
        7'b0000001 : disp=4'h0;
        7'b1001111 : disp=4'h1;
        7'b0010010 : disp=4'h2;
        7'b0000110 : disp=4'h3;
        7'b1001100 : disp=4'h4;
        7'b0100100 : disp=4'h5;
        7'b0100000 : disp=4'h6;
        7'b0001111 : disp=4'h7;
        7'b0000000 : disp=4'h8;
        7'b0001100 : disp=4'h9;
        7'b0001000 : disp=4'hA;
        7'b1100000 : disp=4'hB;
        7'b0110001 : disp=4'hC;
        7'b1000010 : disp=4'hD;
        7'b0110000 : disp=4'hE;
        7'b0111000 : disp=4'hF;
        default : disp=4'bxxxx;
    endcase
end
endfunction

initial
  begin
    $display("%h%h", disp(7'b0000001), disp(7'b0110000)); //expecting 0E
    $finish;
  end
endmodule

Hida · Accepted Answer · 2016-11-18 12:13:22Z

5

You are missing the size of the output from the function. It defaults to 1 bit and because the first bit of 'hE is 0 it returns zero.

Change the function declaration to:

function [3:0] disp;

answered Nov 18, 2016 at 12:13

Hida

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