4-bit counter using logic elements: output is always 0

Question

I am trying to build a 4-bit counter in system Verilog using logical elements only. I am using simple D-flipflops with some XOR and AND logic to achieve this. However, while simulating, the Output values are constantly 0, and I am not sure what's the issue.

Code:

 module d_flipflop (
    input reg Enable,
    input logic clk,
    output reg Out
    );

   always @(posedge clk)
   begin
   Out <= Enable;

   end

endmodule

module Four_bitCounter (
  input reg Enable,
  input logic clk,
  output reg out0, out1, out2, out3
   );

  logic ffInput0;
  logic ffInput1;
  logic ffInput2;
  logic ffInput3;

  always @(*) begin
    ffInput0 <= out0 ^ Enable;
    ffInput1 <= out1 ^ (Enable & out0);
    ffInput2 <= out2 ^ (Enable & out1);
    ffInput3 <= out3 ^ (Enable & out2);
   end


  d_flipflop dff0 (
    .Enable(ffInput0),
    .clk (clk),
    .Out (out0)

      );



     d_flipflop dff1 (
      .Enable(ffInput1),
      .clk (clk),
      .Out (out1)

       );


      d_flipflop dff2 (
       .Enable(ffInput2),
       .clk (clk),
       .Out (out2)

        );


      d_flipflop dff3 (
       .Enable(ffInput3),
       .clk (clk),
       .Out (out3)

        );




  endmodule

TestBench file:

  module Four_bitCounter_tb();

       reg out0, out1, out2, out3;
       logic clk;
       reg Enable;



   Four_bitCounter F_bc0 (
    .Enable(Enable),
    .clk (clk),
    .out0 (out0),
    .out1 (out1),
    .out2 (out2),
    .out3 (out3)
      );

   initial begin
    clk = 0;
    forever #10 clk = ~clk;

     end


     initial begin
      out0 <= 1 'b0;
      out1 <= 1 'b0;
      out2 <= 1 'b0;
      out3 <= 1 'b0;
       Enable <= 1 'b0; 


    #20

     Enable <= 1 'b1;

     #300

    $finish;



     end


     endmodule

Simulation :

Design:

toolic · Accepted Answer · 2021-03-03 13:52:16Z

When I try to compile your code, I get errors with multiple simulators.

In the testbench, the out0 signal has multiple drivers. The same for the other 3 "out" signals. Since they are outputs of the design, you should not make assignments to them in the testbench. Also you should declare them as wire, not reg. Here is the modified testbench:

module Four_bitCounter_tb();
    wire out0, out1, out2, out3;
    logic clk;
    reg Enable;

    Four_bitCounter F_bc0 (
        .Enable(Enable),
        .clk  (clk),
        .out0 (out0),
        .out1 (out1),
        .out2 (out2),
        .out3 (out3)
    );

    initial begin
        clk = 0;
        forever #10 clk = ~clk;
    end

    initial begin
        Enable <= 1'b0; 
        #20
        Enable <= 1'b1;
        #300
        $finish;
    end
endmodule

After that change, I see unknowns (X) on the outputs. This happens because the flipflop Out is X at time 0. All reg types are initialized to X. You need a way to initialize them to 0. For simulations, change:

output reg Out

to:

output reg Out = 0

Alternately, to get rid of unknown values at the start of simulation, you could use a reset signal for your design.

You should sign up for a free account on edaplayground; this will give you access to other simulators where you might get better information about why your simulation misbehaves.

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