Function in verilog

Question

I used the code below as a function in ModelSim, and it raised the error of 'Global declarations are illegal in Verilog 2001 syntax'. could anyone help me with this?

function [24:0] shiftright(input [24:0] in);
integer i;
begin
if (in)
for (i=0; i<25; i=i+1) begin
    if (i == 24) shiftright[i]<= 0;
    else shiftright[i] <= in[i+1];
end
end
endfunction

dave_59 · Accepted Answer · 2021-11-06 06:45:48Z

0

You have written your function outside of a module declaration. All declarations must be inside a module in Verilog. SystemVerilog does allow variables, functions and a number of other things outside of a module.

Also, you cannot use a non-blocking assignment to the return value of a function.

answered Nov 6, 2021 at 6:45

dave_59

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