VHDL Repeat one number to std_logic_vector

Question

I'm new to VHDL and I'm trying to figure out a better way to accomplish the following. For example, I have one std_logic_vector of 2 bits called x and another std_logic_vector of 5 bits called y. I want to assign the first digit of x, which is x(0) to all 5 bits of y. I thought of doing y(0) <= x(0), y(1) <= x(0)... but it's not very convenient. Thanks for your time.

y can be assigned an aggregate whose elements all have the value of x(0). See e.g. IEEE Std 1076-2008 9.3.3 Aggregates, 9.3.3.3 Array aggregates "The index range of an array aggregate that has an others choice shall be determinable from the context. That is, an array aggregate with an others choice shall appear only in one of the following contexts: ... e) As a value expression in an assignment statement, where the target is a declared object (or member thereof), and either the subtype of the target is a fully constrained array subtype or the target is a slice name." — user16145658
– user16145658, Commented Sep 30, 2022 at 20:04
Instead of relying on rote learning how an assignment of an aggregate expression value assignment works is dependent on declarations of objects/values in the expression as well as the target object or slice. Provide a minimal reproducible example. — user16145658
– user16145658, Commented Sep 30, 2022 at 20:38

the busybee · Accepted Answer · 2022-09-30 20:01:58Z

1

You can use this assignment:

    y <= (others => x(0));

answered Sep 30, 2022 at 20:01

the busybee

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1 Comment

user16145658 Over a year ago

Without quantifying what makes the incomplete example assignment statement 'not very convenient' what makes this answer more convenient? Seems the OP and you are dealing with subjective criteria.

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