Elements in the array are not updated at the same time in post-implementation timing simulation

I am trying to write a FSM. A very simple one, which updates its value (0 to 4 and then 0 again) on the posedge of the input SCL.

This is my design source code:

`timescale 1ns / 1ps

module fsm(
    input wire SCL,
    output wire [3:0] state
    );
    reg [3:0] state_drv = 0;
    
    assign state = state_drv;
    
    always@(posedge SCL)begin
        if(state < 4)begin
            state_drv <= state_drv + 1;
        end
        else begin
            state_drv <= 0;
        end        
    end
endmodule

and here is my testbench code

`timescale 1ns / 1ps

module testbench();
    
    reg clk = 0;
    wire [3:0] state;
    wire scl;
    
    always #5 clk = ~clk;
    
    assign scl = clk;
    
    fsm is1(
        .SCL(clk),
        .state(state)
    );
    
    initial begin 
        # 10000 
        $finish;
    end
endmodule

In the post-implementation timing simulation (I use Vivado and its default simulator), I found that the waveform is a little bit different from what I have in mind.

Waveform:

I want the state to change from 01 (1) → 10 (2), but the state transition is 01 → 11 → 10. Looking at the waveform of each element in the array. I think it's because not all the bits change at the same moment.

Is this a common issue or there are problems with my Verilog code?