How can I compare the arrays in VHDL?

Question

I am having problem with comparing the arrays in VHDL, in SysVerilog language it is easy but I couldn't find any solutions for my problem can you help me please ?

It says it is illegal to use other => 1 with array's specific interval. Line 52.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 02.10.2023 18:16:34
-- Design Name: 
-- Module Name: RELU - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ReLU is
  generic (
    dataWidth : integer := 16;
    weightIntWidth : integer := 4
  );
  port (
    PIClk : in std_logic;
    PIRELUInput : in std_logic_vector(2*dataWidth-1 downto 0);
    PORELUOut : out std_logic_vector(dataWidth-1 downto 0)
  );
end entity ReLU;

architecture Behavioral of ReLU is

  constant positive_saturate : std_logic_vector(dataWidth-1 downto 0) := (others => '0');

begin

  process(PIClk)
    variable x_signed : signed(2*dataWidth-1 downto 0);
  begin
    if rising_edge(PIClk) then
    
        x_signed := signed(PIRELUInput);
        
      if x_signed >= 0 then
      
        if x_signed(2*dataWidth-1 downto weightIntWidth) = (others => '1') then -- <<<<<HERE
          PORELUOut <= positive_saturate & '1'; -- Positive saturate
        else
          PORELUOut <= PIRELUInput(dataWidth+weightIntWidth-1 downto weightIntWidth);
        end if;
        
      else
          PORELUOut <= (others => '0'); -- Negative input, output is 0
      end if;
      
    end if;
    
  end process;

end  Behavioral;

I have tried to use the others but it didn't go well.

Matthias Schweikart · Accepted Answer · 2023-10-03 15:36:06Z

1

Correct is:

if x_signed(2*dataWidth-1 downto weightIntWidth)=
           (2*dataWidth-1 downto weightIntWidth => '1') then

answered Oct 3, 2023 at 15:36

Matthias Schweikart

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2 Comments

Tricky Over a year ago

another "correct" answer from VHDL 2008 is: if and x_signed(2*dataWidth-1 downto weightIntWidth) = '1' then

rhall Over a year ago

@Tricky in VHDL 2008 you should be able to leave the = '1' part out and rely on the ?? operator for automatic conversion to boolean

user22679688 · Accepted Answer · 2023-10-04 22:03:45Z

The reason why the others choice is not allowed here is that while the type is known from context the subtype (here, number of elements) is not. The reason for that is that the equality relational operator can operate between array values of different lengths, there is no rule that specifies the right hand operand has the same length of the left hand.

The others choice can be used in an aggregate that is in a qualified expression:

  process (PIClk)
    variable x_signed : signed(2*dataWidth-1 downto 0);
    subtype x_pref is signed (2 * dataWidth - 1 downto weightIntWidth);
  begin
    if rising_edge(PIClk) then
    
        x_signed := signed(PIRELUInput);
        
      if x_signed >= 0 then
      
        -- if x_signed(2*dataWidth-1 downto weightIntWidth) = (others => '1') then -- <<<<<HERE
        if x_signed(x_pref'range) = x_pref'(others => '1') then
          PORELUOut <= positive_saturate & '1'; -- Positive saturate
        else
          PORELUOut <= PIRELUInput(dataWidth+weightIntWidth-1 downto weightIntWidth);
        end if;
        
      else
          PORELUOut <= (others => '0'); -- Negative input, output is 0
      end if;
      
    end if;
    
  end process;

where the subtype is explicitly supplied by the qualified expression and the aggregate is allowed to contain an others choice.

You'll also find that the second if statement condition can never be TRUE:

      if x_signed >= 0 then
      
        -- if x_signed(2*dataWidth-1 downto weightIntWidth) = (others => '1') then -- <<<<<HERE
        if x_signed(x_pref'range) = x_pref'(others => '1') then

while right hand operand is all '1's. The type from context is signed and a MSB of '1' for a two's complement value represents a negative number or less that zero.

That begs the question of why you are doing numeric value comparison here.

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