I am wondering if there is any difference between these two connections, I know the first case can accept default value, but my question is rather from a netlist point of view :
module test(input clk);
endmodule
module top();
test i_test();
endmodule
2- Intentionally unconnected
module test(input clk);
endmodule
module top();
test i_test(.clk());
endmodule
Thank you
The difference is solely positional versus explicitly named port connections. It has nothing to do with being connected or unconnected. (i.e. there is no functional difference).
Explicitly named port connections are highly recommended especially when you intend to leave some ports unconnected. It reduces the chance of misaligning ports by position.
Is there any difference between these two connections ... from a netlist point of view
Netlists are generated by synthesis tools.
There is no behavioral or structural difference between the two Verilog code snips in the post WRT netlist generation output of synthesis tools. They will both generate the same empty post synthesis netlist. No logic is inferred in both cases.
You should get a different set of warnings from each in synthesis.
