I was running a test case for iverilog provided at this link and had posted a question earlier. When I tested iverilog with uart test case further, found that in uart_tb.v, we are using file uart_port.sv which is s system verilog file and contain a system verilog keyword "interface". Below is the file.
uart_ports.sv:
`ifndef UART_PORTS_SV
`define UART_PORTS_Sv
interface uart_ports(
output logic reset ,
input wire txclk ,
output logic ld_tx_data ,
output logic [7:0] tx_data ,
output logic tx_enable ,
output logic tx_out ,
input wire tx_empty ,
input wire rxclk ,
output logic uld_rx_data ,
input wire [7:0] rx_data ,
output logic rx_enable ,
output logic rx_in ,
input wire rx_empty ,
output logic loopback ,
output logic rx_tb_in
);
endinterface
`endif
My question is, does iverilog support system verilog keywords? I can use different version of verilog i.e. verilog 1995, 2001 and 2005 with -g flag, and I tried with -g2005, but still get the error:
uart_ports.v:4: syntax error
Is there any keyword for interface keyword (of System verilog) in verilog or should I consider that either this test case can't be simulated with iverilog or iverilog limitation with System verilog keywords.
