Verilog : Memory block Instantiation

Question

I used the following code to instantiate 2-D memory in a verilog

reg  [15:0] data_pattern_even [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF};

reg  [15:0] data_pattern_ev [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF};

This instantiation worked all right in Simulation but failed to work when actually synthesised and RTL analysis done

Can anyone elaborate to me as in how that is possible?

No error . Just that in the RTL , all vaues of data_pattern_even arent FFFF . 1st one is FFFF and rest all are zero — Ananth Krishna
– Ananth Krishna, Commented Jun 17, 2016 at 9:07
FPGA or ASIC synthesis? if FPGA can you list which FPGA and tool versions your using. — Morgan
– Morgan, Commented Jun 17, 2016 at 9:15
artix - 7 xc7a35 and vivado 2014.2 . I heard from my friend that initialization in verilog has to be done on certain condition e.g reset . might that be the reason ? — Ananth Krishna
– Ananth Krishna, Commented Jun 17, 2016 at 9:38
See UG901 for how to describe RAMs and ROMs for Xilinx Vivado synthesis in Verilog (or VHDL). — Paebbels
– Paebbels, Commented Jun 17, 2016 at 12:50

Community · Accepted Answer · 2017-05-23 10:28:52Z

3

For Altera devices: https://www.altera.com/support/support-resources/design-examples/design-software/verilog/ver_ram.html

For Xilinx devices (as given by Paebbels): http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug901-vivado-synthesis.pdf (Chapter 3, "Initializing RAM Contents")

For Lattice devices: http://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/EI/iCEcube2_2013-08_userguide.pdf?document_id=50165 ("Initializing Inferred RAM")

For Microsemi devices: http://www.microsemi.com/document-portal/doc_view/129865-ac162-ram-initialization-and-rom-emulation-in-proasic-sup-u-plus-u-sup-devices-app-note

A short search with google and I found this: How to initialize contents of inferred Block RAM (BRAM) in Verilog

Just google it :-)

edited May 23, 2017 at 10:28

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answered Jun 19, 2016 at 9:23

Oron Port

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