Insert "begin" after if statement in Emacs Verilog Mode

Question

I have been using Emacs to create and modify Verilog codes for some time now. However, in Verilog mode, I am facing a small issue when I try to insert an "if" statement using the emacs command:

C-c C-t ?

The following is an example of how the statement is created in the above scenario:

if (a<b) begin
// the rest of the code

However I need emacs to insert the "begin" in the next line as shown below:

if (a<b)
begin
//rest of the code

After digging through the Verilog customization options available, I found one option named Verilog Indent Begin After If which I think is supposed to produce the above effect. However toggling this option did not give my any visible changes.

Any help would be greatly appreciated.

Why not just hack up your own command based on what you see in verilog-mode and add it to the keymap? — pmr
– pmr, Commented Aug 7, 2012 at 12:49
@pmr: Ya thats true but unfortunately I have no experience in lisp programming :( I was looking whether verilog mode had any direct options for the same. If not, I guess I will have to cook up something myself :/ — Pulimon
– Pulimon, Commented Aug 7, 2012 at 12:51
I tried to provide you with everything you need. Have a look at the documentation of skeletons to understand them better. You probably want to stay away from the key-map part until you are a little more fluent in elisp. C-h f and C-h v are your friends. — pmr
– pmr, Commented Aug 7, 2012 at 13:03
Thanks. I think I will spend some time reading up on elisp as you suggested. :) — Pulimon
– Pulimon, Commented Aug 7, 2012 at 13:15

pmr · Accepted Answer · 2012-08-07 13:01:42Z

3

Looking at the code you will see that the function:

(define-skeleton verilog-sk-if
  "Insert a skeleton if statement."
  > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n
  > _ \n
  > (- verilog-indent-level-behavioral) "end " \n )

actually defines a skeleton. Just copy paste and add another line-break:

(define-skeleton my-verilog-sk-if
  "Insert a skeleton if statement."
  > "if (" '(verilog-sk-prompt-condition) & ")" \n " begin" \n
  > _ \n
  > (- verilog-indent-level-behavioral) "end " \n )

now we just need to hook our function over the old one in verilog-mode:

(add-hook 'verilog-mode-hook
          '(lambda ()
             ;; this is quite the hack because we don't respect
             ;; the usual prefix of verilog-mode but sufficient for us
             (define-key verilog-mode-map "\C-c\C-t?"
                         'my-verilog-sk-if)))

answered Aug 7, 2012 at 13:01

pmr

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1 Comment

pmr Over a year ago

@event_jr Yes, that could be a replacement. Unfortunately, yas is not part of Emacs core and so core packages like verilog can not rely on it. Also, when you already have the boilerplate, why go and change anything? ;)

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