Suppose I have an array like this:
parameter n=100;
reg array[0:n-1];
How would one get the logic-OR value of each and every bit in the array? The resulted circuit must be combinatorial.
This is a follow up question from this one. (see discussion below the answer)
I don't know if this meets your design requirements, but you might have a much easier time with a hundred bit bus reg [n-1:0] array; than by using an array of 1 bit wires. Verilog does not have the greatest syntax to support arrays. If you had a bus instead you could just do assign result = |array;
If you must use an array, than I might consider first turning it into a bus with a generate loop, and then doing the same:
parameter n=100;
reg array[0:n-1];
wire [n-1:0] dummywire;
genvar i;
generate
for (i = 0; i < n; i = i+1) begin
assign dummywire[i] = array[i];
end
endgenerate
assign result = |dummywire;
I'm not aware of a more elegant way to do this on arrays.
reg [9:0] packed;and an unpacked array isreg unpacked [0:9];. I got that but what are the differences between the two?reg [9:0] packed;will be accessed as a single value whereasreg unpacked [9:0]cannot. Sopacked = 6;is valid butunpacked = 6;is not. I should have noted that packed/unpacked are SystemVerilog terms but the concept is the same in Verilog.