What is wrong in this verilog code?

Question

I'm studying verilog and trying to apply the concepts in my fpga. It supossed to work in this way : When Switch 1 is on, all red leds turn on. When Switch 2 is on, all green leds turn on. When Switch 3 is on, all leds turn on. The problem is when I put it in my fpga switch . Could someone tell me why? Here's my code :

module LED (

    input CLOCK_50,
    input [17:0] SW,
    output reg [17:0] LEDR,
    output reg [9:0] LEDG
);

always@(posedge(CLOCK_50))

    begin
        case(SW[0])
            0:
                LEDR = 0;
            1: 
                LEDR = ~LEDR;
        endcase

        case(SW[1])
            0:
                LEDG = 0;
            1:
                LEDG = ~LEDG;
        endcase 
        case(SW[2])
            0:
                begin
                    LEDR = 0;
                    LEDG = 0;
                end
            1:
                begin
                    LEDR = ~LEDR;
                    LEDG = ~LEDG;
                end
        endcase 

    end
endmodule

you have to analize all case. what happend if sw 1 and sw 2 is on? and sw1 sw2 and sw3 is on? and other case? — inye
– inye, Commented May 25, 2015 at 2:15
additionally, use non-blocking assignments (<=) instead of blocking assignments (=) when assigning values in edge-triggered always blocks. — wilcroft
– wilcroft, Commented May 25, 2015 at 2:58
additionally, using constructs like LEDR = ~LEDR; will result with blinking diodes (with frequency equals to clock frequency) — Qiu
– Qiu, Commented May 25, 2015 at 8:36
@Bruno the intensity is because with ~LEDR in each posedge clk you toggle the value. Then the led is 50% on and 50% off and you only can see low intensity because our eyes can see htis fecuency — inye
– inye, Commented May 25, 2015 at 12:20

inye · Accepted Answer · 2015-05-25 15:40:14Z

1

Some problems in the code are:

for this situation is best with non-blocking assign. Explication 1 2
you are reassigning LEDR and LEDG with the case(SW[2]) statement
You are toggling the values of LEDG and LEDR on each posedge(CLOCK_50). this is the reason why you see low intensity in leds.

tips:

you can use bit notation (also hex) like LEDG = 10'b1111111111; or LEDG = 10'b1111_1111_11; (hex: 10'h3AA)

you can use a case for the SW like:

case(SW)
    3'b000:
        ...
    3'b001:
        ...
    3'b010:
        ...
    3'b100:
        ...
    default:
        ...

answered May 25, 2015 at 15:40

inye

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